Automatic Formal Synthesis of Hardware from Higher Order Logic

Authors:
Mike Gordon;Juliano Iyoda;Scott Owens;Konrad Slind
Affiliations:
University of Cambridge Computer Laboratory, William Gates Building, JJ Thomson Avenue, Cambridge CB3 0FD, UK;University of Cambridge Computer Laboratory, William Gates Building, JJ Thomson Avenue, Cambridge CB3 0FD, UK;University of Utah, School of Computing, 50 South Central Campus Drive, Salt Lake City, Utah UT84112, USA;University of Utah, School of Computing, 50 South Central Campus Drive, Salt Lake City, Utah UT84112, USA
Venue:
Electronic Notes in Theoretical Computer Science (ENTCS)
Year:
2006

Citing 8
Cited 6

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Abstract

A compiler that automatically translates recursive function definitions in higher order logic to clocked synchronous hardware is described. Compilation is by mechanised proof in the HOL4 system, and generates a correctness theorem for each function that is compiled. Logic formulas representing circuits are synthesised in a form suitable for direct translation to Verilog HDL for simulation and input to standard design automation tools. The compilation scripts are open and can be safely modified: synthesised circuits are correct-by-construction. The synthesisable subset of higher order logic can be extended using additional proof-based tools that transform definitions into the subset.