Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Partial evaluation and automatic program generation
Partial evaluation and automatic program generation
Parameterised processor generation
Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs
The Chinook hardware/software co-synthesis system
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Lava: hardware design in Haskell
ICFP '98 Proceedings of the third ACM SIGPLAN international conference on Functional programming
A Transformation System for Developing Recursive Programs
Journal of the ACM (JACM)
The Definition of Standard ML
A Statically Allocated Parallel Functional Language
ICALP '00 Proceedings of the 27th International Colloquium on Automata, Languages and Programming
Generating Netlists from Executable Circuit Specifications
Proceedings of the 1992 Glasgow Workshop on Functional Programming
muFP, a language for VLSI design
LFP '84 Proceedings of the 1984 ACM Symposium on LISP and functional programming
Functional Design Using Behavioural and Structural Components
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
A Higher-Level Language for Hardware Synthesis
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Hardware Synthesis Using SAFL and Application to Processor Design
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
SAS '01 Proceedings of the 8th International Symposium on Static Analysis
Development and Application of Design Transformations in ForSyDe
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Automatic Formal Synthesis of Hardware from Higher Order Logic
Electronic Notes in Theoretical Computer Science (ENTCS)
Low-level programming in Hume: an exploration of the HW-Hume level
IFL'06 Proceedings of the 18th international conference on Implementation and application of functional languages
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In previous work we have developed and prototyped a silicon compiler which translates a functional language (SAFL) into hardware. Here we present a SAFL-level program transformation which: (i) partitions a specification into hardware and software parts and (ii) generates a specialised architecture to execute the software part. The architecture consists of a number of interconnected heterogeneous processors. Our method allows a large design space to be explored by systematically transforming a single SAFL specification to investigate different points on the area-time spectrum.