Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Constrained resource sharing and conflict resolution in Hebe
Integration, the VLSI Journal
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
A Transformation System for Developing Recursive Programs
Journal of the ACM (JACM)
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
The Definition of Standard ML
IEEE Design & Test
A Statically Allocated Parallel Functional Language
ICALP '00 Proceedings of the 27th International Colloquium on Automata, Languages and Programming
Hardware/Software Co-Design Using Functional Languages
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
A Higher-Level Language for Hardware Synthesis
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Static Analyses for Eliminating Unnecessary Synchronization from Java Programs
SAS '99 Proceedings of the 6th International Symposium on Static Analysis
HardwareC -- A Language for Hardware Design (Version 2.0)
HardwareC -- A Language for Hardware Design (Version 2.0)
Functional Design Using Behavioural and Structural Components
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
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Hardware designs typically combine parallelism and resourcesharing; a circuit's correctness relies on shared resources being accessed mutually exclusively. Conventional high-level synthesis systems guarantee mutual exclusion by statically serialising access to shared resources during a compile-time process called scheduling. This approach suffers from two problems: (i ) there is a large class of practical designs which cannot be scheduled statically; and (ii) a statically fixed schedule removes some opportunities for parallelism leading to less efficient circuits. This paper surveys the expressivity of current scheduling methods and presents a new approach which alleviates the above problems: first scheduling logic is automatically generated to resolve contention for shared resources dynamically; then static analysis techniques remove redundant scheduling logic. We call our method Soft Scheduling to highlight the analogy with Soft Typing: the aim is to retain the flexibility of dynamic scheduling whilst using static analysis to remove as many dynamic checks as possible.