Selected papers of the Second Workshop on Concurrency and compositionality
Lava: hardware design in Haskell
ICFP '98 Proceedings of the third ACM SIGPLAN international conference on Functional programming
HML, a novel hardware description language and its translation to VHDL
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Asynchronous exceptions in Haskell
Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation
The Definition of Standard ML
A Statically Allocated Parallel Functional Language
ICALP '00 Proceedings of the 27th International Colloquium on Automata, Languages and Programming
Hardware/Software Co-Design Using Functional Languages
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Hardware Synthesis from Term Rewriting Systems
VLSI '99 Proceedings of the IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration: Systems on a Chip
muFP, a language for VLSI design
LFP '84 Proceedings of the 1984 ACM Symposium on LISP and functional programming
Microprocessor Specification in Hawk
ICCL '98 Proceedings of the 1998 International Conference on Computer Languages
HardwareC -- A Language for Hardware Design (Version 2.0)
HardwareC -- A Language for Hardware Design (Version 2.0)
Hardware Synthesis Using SAFL and Application to Processor Design
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
SAS '01 Proceedings of the 8th International Symposium on Static Analysis
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We describe SAFL+: a call-by-value, parallel language in the style of ML which combines imperative, concurrent and functional programming. Synchronous channels allow communication between parallel threads and π-calculus style channel passing is provided. SAFL+ is designed for hardware description and synthesis; a silicon compiler, translating SAFL+ into RTL-Verilog, has been implemented. By parameterising functions over both data and channels the SAFL+ fun declaration becomes a powerful abstraction mechanism unifying a range of structuring techniques treated separately by existing HDLs. We show how SAFL+ is implemented at the circuit level and define the language formally by means of an operational semantics.