Sizing synchronization queues: a case study in higher level synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Hardware/software synthesis of formal specifications in codesign of embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An algorithm to determine mutually exclusive operations in behavioral descriptions
Proceedings of the conference on Design, automation and test in Europe
AGENDA: an attribute grammar driven enviornment for the design automation of digital systems
Proceedings of the conference on Design, automation and test in Europe
Superlog, a unified design language for system-on-chip
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
High-level specification and efficient implementation of pipelined circuits
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
IEEE Design & Test
Using VHDL for High-Level, Mixed-Mode System Simulation
IEEE Design & Test
Introduction to High-Level Synthesis
IEEE Design & Test
Using a Programming Language for Digital System Design
IEEE Design & Test
Specification and Validation of Control-Intensive IC's in hopCP
IEEE Transactions on Software Engineering
A Higher-Level Language for Hardware Synthesis
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Hardware Synthesis Using SAFL and Application to Processor Design
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
SAS '01 Proceedings of the 8th International Symposium on Static Analysis
Approach to the Synthesis of HW and SW in Codesign
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
An Algorithm for Direct Synthesis of Formal Specifications
RSP '97 Proceedings of the 8th International Workshop on Rapid System Prototyping (RSP '97) Shortening the Path from Specification to Prototype
Synchronization of communicating modules and processes in high level synthesis
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
A methodology for generating verified combinatorial circuits
Proceedings of the 4th ACM international conference on Embedded software
The Challenges of Hardware Synthesis from C-Like Languages
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Application of the object-oriented principles for hardware and embedded system design
Integration, the VLSI Journal
The Challenges of Synthesizing Hardware from C-Like Languages
IEEE Design & Test
Verification of SpecC using predicate abstraction
Formal Methods in System Design
A code refinement methodology for performance-improved synthesis from C
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
EURASIP Journal on Applied Signal Processing
CHiMPS: a high-level compilation flow for hybrid CPU-FPGA architectures
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Safety shell for specification-PEARL oriented UML real-time projects
Computer Languages, Systems and Structures
Performance and power of cache-based reconfigurable computing
Proceedings of the 36th annual international symposium on Computer architecture
A Force-Directed Scheduling based architecture generation algorithm and design tool for FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
Standards for system level design
Proceedings of the International Conference on Computer-Aided Design
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High-level synthesis is the transformation from a behavioral level specification of hardware, through a series of optimizations and translations, to an implementation in terms of logic gates and registers. The success of a high-level synthesis system is heavily dependent on how effectively the high-level language captures the ideas of the designer in a simple and understandable way. Furthermore, as system-level issues such as communication protocols and design partitioning dominate the design process, the ability to specify constraints on the timing requirements and resource utilization of a design is necessary to ensure that the design can integrate with the rest of the system. In this paper, a hardware description language called HardwareC is presented. HardwareC supports both declarative and procedural semantics, has a C-like syntax, and is extended with notion of concurrent processes, message passing, timing constraints via tagging, resource constraints, explicit instantiation of models, and template models. The language is used as the input to the Hercules High-level Synthesis System.