Sizing synchronization queues: a case study in higher level synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Optimal synthesis of multichip architectures
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Communicating sequential processes
Communications of the ACM
HardwareC -- A Language for Hardware Design (Version 2.0)
HardwareC -- A Language for Hardware Design (Version 2.0)
High-level Synthesis of Multi-process Behavioral Descriptions
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Conflict analysis in multiprocess synthesis for optimized system integration
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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In ASIC designs, reuse of already available components is often preferred. Synthesis systems catering to this need must ensure proper synchronization among the communicating modules. This paper proposes an object oriented design framework to support reuse. The steps to be taken for synchronization of communicating hardware entities through a non-blocking channel have been analyzed. The synthesis system ensures synchronization among the communicating modules before scheduling. The scheme has been tested on a few real life image processing examples.