The Omega test: a fast and practical integer programming algorithm for dependence analysis
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Synthesis of multiple process digital systems
Synthesis of multiple process digital systems
Multiple-process behavioral synthesis for mixed hardware-software systems
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Synthesis of systems specified as interacting VHDL processes
Integration, the VLSI Journal
Synchronous parallel controller synthesis from behavioural multiple-process VHDL description
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Resource sharing in hierarchical synthesis
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Resource contrained modulo scheduling with global resource sharing
Proceedings of the 11th international symposium on System synthesis
Synchronization detection for multi-process hierarchical synthesis
Proceedings of the 11th international symposium on System synthesis
Time constrained modulo scheduling with global resource sharing
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Worst-case performance analysis of parallel, communicating software processes
Proceedings of the tenth international symposium on Hardware/software codesign
Synchronization of communicating modules and processes in high level synthesis
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Communication Analysis for System-On-Chip Design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Analysis and synthesis of concurrent digital circuits using control-flow expressions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Codex-dp: co-design of communicating systems using dynamic programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Resource budgeting for Multiprocess High-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a novel approach for multiprocess synthesis supporting well-tailored module integration at system level. The goal is to extend the local scope of existing architectural synthesis approaches in order to apply global optimization techniques across process bounds for shared system resources (e.g. memories, busses, global ALUs) during scheduling and binding. This allows an area efficient implementation of un-timed or cycle-fixed multiprocess specifications at RT or algorithmic level of abstraction. Furthermore, this approach supports environment-oriented synthesis for optimized module integration by scheduling accesses to global resources with respect to the access schedules of other modules communicating to the same global resources. As a result, dynamic access conflicts can be avoided by construction, and hence, there is no need for dynamic arbitration of bus and memory accesses with potentially unpredictable timing behavior.