Adaptation of partitioning and high-level synthesis in hardware/software co-synthesis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Synthesis of VHDL concurrent processes
EURO-DAC '94 Proceedings of the conference on European design automation
Incremental hardware estimation during hardware/software functional partitioning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synthesis of multiple process digital systems
Synthesis of multiple process digital systems
A Model and Methodology for Hardware-Software Codesign
IEEE Design & Test
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Execution-time profiling for multiple-process behavioral synthesis
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
The design of mixed hardware/software systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Exploration of hardware/software design space through a codesign of robot arm controller
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Synthesis from mixed specifications
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Hardware/software partitioning of VHDL system specifications
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
A hardware/software partitioner using a dynamically determined granularity
DAC '97 Proceedings of the 34th annual Design Automation Conference
Java as a specification language for hardware-software systems
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Hardware/software synthesis of formal specifications in codesign of embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multi-thread graph: a system model for real-time embedded software synthesis
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Process Partitioning for Distributed Embedded Systems
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
The Interplay of Run-Time Estimation and Granularity in HW/SW Partitioning
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Automatic Generation of a Real-Time Operating System for Embedded Systems
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
An Approach to Mixed Systems Co-Synthesis
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
High-level Synthesis of Multi-process Behavioral Descriptions
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Partitioning of embedded applications onto heterogeneous multiprocessor architectures
Proceedings of the 2003 ACM symposium on Applied computing
Conflict analysis in multiprocess synthesis for optimized system integration
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Affinity-Driven System Design Exploration for Heterogeneous Multiprocessor SoC
IEEE Transactions on Computers
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Hardware/Software Co-Design Methodology for Design of Embedded Systems
Integrated Computer-Aided Engineering
Finding optimal hardware/software partitions
Formal Methods in System Design
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Abstract: Systems composed of microprocessors interacting with ASICs are necessarily multiple-process systems, since the controller in the microprocessor is separate from any controllers on the ASIC. For this reason, the design of such systems offers an opportunity to exploit not only hardware-software tradeoffs, but concurrency tradeoffs as well. The paper describes an automated iterative improvement technique for performing concurrency optimization and hardware-software tradeoffs simultaneously. Experimental results illustrate that addressing these two issues simultaneously enables us to identify a number of interesting cost/performance points that would not have been found otherwise.