Field-programmable gate arrays
Field-programmable gate arrays
GENOA: a customizable language- and front-end independent code analyzer
ICSE '92 Proceedings of the 14th international conference on Software engineering
Efficient flow-sensitive interprocedural computation of pointer-induced aliases and side effects
POPL '93 Proceedings of the 20th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Multiple-process behavioral synthesis for mixed hardware-software systems
ISSS '95 Proceedings of the 8th international symposium on System synthesis
An introduction to genetic algorithms
An introduction to genetic algorithms
Data-flow assisted behavioral partitioning for embedded systems
DAC '97 Proceedings of the 34th annual Design Automation Conference
Transformational partitioning for co-design of multiprocessor systems
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
COSYN: hardware-software co-synthesis of heterogeneous distributed embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Graph based communication analysis for hardware/software codesign
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
CMAPS: a cosynthesis methodology for application-oriented parallel systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
System synthesis for multiprocessor embedded applications
DATE '00 Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Parallel and Distributed Systems
An efficient architecture model for systematic design of application-specific multiprocessor SoC
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 38th annual Design Automation Conference
Dynamic modeling of inter-instruction effects for execution time estimation
Proceedings of the 14th international symposium on Systems synthesis
Modeling assembly instruction timing in superscalar architectures
Proceedings of the 15th international symposium on System Synthesis
IEEE Transactions on Software Engineering
Graph Layout through the VCG Tool
GD '94 Proceedings of the DIMACS International Workshop on Graph Drawing
Metrics for design space exploration of heterogeneous multiprocessor embedded systems
Proceedings of the tenth international symposium on Hardware/software codesign
Functional Partitioning for Low Power Distributed Systems of Systems-on-a-chip
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Reconfigurable Architectures for General-Purpose Computing
Reconfigurable Architectures for General-Purpose Computing
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Partitioning of embedded applications onto heterogeneous multiprocessor architectures
Proceedings of the 2003 ACM symposium on Applied computing
An area estimation methodology for FPGA based designs at systemc-level
Proceedings of the 41st annual Design Automation Conference
CODEF: a system level design space exploration tool
ICASSP '01 Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference - Volume 02
COHRA: hardware-software cosynthesis of hierarchical heterogeneous distributed embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Codex-dp: co-design of communicating systems using dynamic programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Static power modeling of 32-bit microprocessors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SIERA: a unified framework for rapid-prototyping of system-level hardware and software
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Ad-hoc HW/SW architectures for DBMSs: a co-design approach
AIKED'07 Proceedings of the 6th Conference on 6th WSEAS Int. Conf. on Artificial Intelligence, Knowledge Engineering and Data Bases - Volume 6
WSEAS Transactions on Computers
| Hi-index | 14.98 |
Continuous advances in silicon technology enable the development of complex System-on-Chip as cooperation among Digital Signal Processors (DPSs), General Purpose Processors (GPPs), and specific hardware components. The impact of this choice is not only limited to the target architecture, but also encompasses the overall system specification. It is thus crucial to manage such a complexity using high-level specification languages and a tool chain supporting the designer throughout a set of strategic decisions, such as the identification of a set of possible target architectures, the verification of the correctness of the specification, and the partitioning of the specification onto a set of computational resources. This paper addresses this type of problem by proposing a design flow supporting the system-level design of heterogeneous multiprocessor system-on-chip (MP-SoC), by extracting information from the system description (e.g., SystemC)—statically and in a fast manner—and by providing a set of quantitative measures correlating the type of executor, the functionality, and a timing estimation. Partitioning and architecture selection are built on top of this data and the final analysis of the selected Hardware-Software solution over the identified candidates is finally submitted to a timing verification via simulation. Note that the possibility of actually performing a comprehensive design space exploration, in general, is tightly influenced by the interaction between partitioning/architecture-selection and timing simulation in the design flow; for this reason, the description of this aspect is particularly emphasized in the presentation of the methodology. To show the applicability of the proposed methodology, two relevant case studies are described in the paper.