Adaptive multi-constraints in hardware-software partitioning for embedded multiprocessor FPGA systems

Authors:
Trong-Yen Lee;Yang-Hsin Fan;Chia-Chun Tsai
Affiliations:
Graduate Institute of Computer and Communication, National Taipei Univ. of Technology, Taipei, Taiwan, ROC;Graduate Institute of Computer and Communication, National Taipei Univ. of Technology, Taipei, Taiwan, ROC and Dept. of Computer Science and Information Eng., National Taitung Univ., Taitung, Taiw ...;Dept. of Computer Science and Information Eng., Nanhua Univ., Chia-Yi, Taiwan, ROC
Venue:
WSEAS Transactions on Computers
Year:
2009

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Abstract

An embedded multiprocessor field programmable gate array (FPGA) system has a powerful and flexible architecture that the interaction between hardware circuits and software applications. Modern electronic products, such as portable devices, consumer electronics and telematics, can be evaluated rapidly in this platform via the implementation of a set of hardware and software tasks. However, the functionality is markedly increased, resulting in a significant raise in the number of hardware and software tasks. Consequently, too large of a solution space is formed to achieve hardware-software partitioning. Moreover, a partitioning result with low power consumption and fast execution time is difficult to obtain since meeting simultaneously multi-constraints from hundreds of thousands of combinations of hardware-software partitions is difficult. Thus, this work presents a hardware-software partitioning scheme that can obtain a partitioning result that satisfies multi-constraints from massive solution space. Specifically, this study attains a partitioning result with low power consumption and fast execution time. The effectiveness of the proposed approach is demonstrated by assessing a JPEG encoding system and a benchmark with 199 tasks.