Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Sizing synchronization queues: a case study in higher level synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Synthesis and simulation of digital systems containing interacting hardware and software components
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Specification and design of embedded systems
Specification and design of embedded systems
Sizing and verification of communication buffers for communicating processes
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Buffer assignment for data driven architectures
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Graph Algorithms
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Journal of VLSI Signal Processing Systems
Codesign of embedded systems: status and trends
Readings in hardware/software co-design
Codesign of Embedded Systems: Status and Trends
IEEE Design & Test
Partitioning of embedded applications onto heterogeneous multiprocessor architectures
Proceedings of the 2003 ACM symposium on Applied computing
Affinity-Driven System Design Exploration for Heterogeneous Multiprocessor SoC
IEEE Transactions on Computers
Application partitioning on programmable platforms using the ant colony optimization
Journal of Embedded Computing - Embeded Processors and Systems: Architectural Issues and Solutions for Emerging Applications
| Hi-index | 0.00 |
In this paper we present a novel compiler-directed approach tosystem-level partitioning for a given description of system functionalityin a hardware description language (HDL). The algorithmis based on a definition-use analysis of the storage in the systemmodel to ensure that the resulting portions can be implemented in aloosely-coupled multi-rate execution model with minimal synchronizationbetween the portions. The cost of the hardware-softwareinterface, in terms of amount of buffering required, is computed accuratelyas a part of the partitioning cost function using a data-flowreaching analysis. The proposed algorithm has been implementedand experimental results show up to 65% improvement in buffersizes over the min-cut partitioning algorithm.