A Specification Refinement Methodology for Power Efficient Partitioning of Data-Dominated Algorithms Within Performance Constraints

  • Authors:

  • K. Masselos;K. Danckaert;F. Catthoor;N. Zervas;C. E. Goutis;H. De Man

  • Affiliations:

  • VLSI Design Laboratory, Department of Electrical and Computer Engineering, University of Patras, Rio 26500, Greece&semi/ IMEC, Kapeldreef 75, B 3001 Leuven, Belgium;IMEC, Kapeldreef 75, B 3001 Leuven, Belgium&semi/ Research Assistant of the Fund for Scientific Research - Flauders;IMEC, Kapeldreef 75, B 3001 Leuven, Belgium&semi/ Katholieke Univ. Leuven, Belgium;VLSI Design Laboratory, Department of Electrical and Computer Engineering, University of Patras, Rio 26500, Greece;VLSI Design Laboratory, Department of Electrical and Computer Engineering, University of Patras, Rio 26500, Greece;IMEC, Kapeldreef 75, B 3001 Leuven, Belgium&semi/ Katholieke Univ. Leuven, Belgium

  • Venue:
  • Journal of VLSI Signal Processing Systems
  • Year:
  • 2000

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Abstract

A specification refinement methodology for the power efficient partitioning of real-time data-dominated algorithms is presented. The main idea of the proposed methodology is the reorganization with respect to data transfer and storage of the initial description of the target algorithm before conventional partitioning. This is achieved through the application of data transfer and storage optimizing high-level code transformations to the initial description of the target algorithm. These transformations basically align the data production and consumption between the different procedures of the initial specification thus reducing the memory size requirements of the system's realizations especially those in the interfaces between different processors. In this way the data transfer and storage related power consumption which forms an important part of the total power budget of a data dominated system is significantly reduced. Performance issues are explicitly taken into account during the application of the data transfer and storage high-level transformations. The proposed methodology can be applied both in a parallel (programmable) processor context and also in heterogeneous hardware-software architectures. The proposed methodology can be also used for the power efficient implementation of data dominated algorithms on architectures based on programmable cores and application specific memory hierarchies. Experimental results from real life applications prove the impact of the proposed methodology.