VLSI image processing
Low-power architectural design methodologies
Low-power architectural design methodologies
Design of a low power video decompression chip set for portable applications
Journal of VLSI Signal Processing Systems - Special issue on technologies for wireless computing
Instruction level power analysis and optimization of software
Journal of VLSI Signal Processing Systems - Special issue on technologies for wireless computing
A low power architecture for wireless multimedia systems: lessons learned from building a power hog
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Journal of VLSI Signal Processing Systems - Special issue on systematic trade-off analysis in signal processing systems design
VLSI Video - Image Signal Processing
VLSI Video - Image Signal Processing
Architectural approaches for video compression
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
MTDT '95 Proceedings of the 1995 IEEE International Workshop on Memory Technology, Design and Testing
Low-power data transfer and storage exploration for H.263 video decoder system
IEEE Journal on Selected Areas in Communications
IEEE Transactions on Circuits and Systems for Video Technology
Global multimedia system design exploration using accurate memory organization feedback
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
System-level power optimization: techniques and tools
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Journal of VLSI Signal Processing Systems - Special issue on system level design
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DCT-Domain Embedded Memory Compression for Hybrid Video Coders
Journal of VLSI Signal Processing Systems - Special issue on recent advances in the design and implementation of signal processing systems
Journal of VLSI Signal Processing Systems
Proceedings of the conference on Design, automation and test in Europe
Power and Speed-Efficient Code Transformation of Video Compression Algorithms for RISC Processors
Journal of VLSI Signal Processing Systems - Special issue on multimedia signal processing
Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Cost-Efficient C-Level Design of an MPEG-4 Video Decoder
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
High-level algorithmic complexity evaluation for system design
Journal of Systems Architecture: the EUROMICRO Journal
EURASIP Journal on Applied Signal Processing
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
ESVD: an integrated energy scalable framework for low-power video decoding systems
EURASIP Journal on Wireless Communications and Networking - Special issue on multimedia communications over next generation wireless networks
Reconfigurable microarchitecture based system-level dynamic power management soc platform
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Hi-index | 0.00 |
A battery powered multimedia communication device requires avery energy efficient implementation. The required efficiencycan only be acquired by careful optimization at all levels ofthe design. System-level power optimizations have a dramatic impacton the overall power budget. We have proposeda system-level step-wise methodology to reduce the power in hardwarerealizations of data-dominated applications, which is partly supportedwith our ATOMIUM environment. In this paper, we extend the methodology tothe realization of embedded software on processor cores.Starting from a high level algorithm description (e.g., in C),a set of optimizations gradually refine the code and thecorresponding memory organization of the array data types.These array data types represent a fully detailed optimized data storage and transfer organization.Instead of creating the physical memories, a mapping can be done eitheron a general memory architecture, including a cache, or on a custom memory architecture.First, typical optimizations addressed by our methodology are applied on a didactical example.The effectiveness of this methodology is then demonstratedby the optimization of two complex applications in an embedded processorcontext: a MPEG2 and a H.263 video decoder.The impact of the power optimizations on the typical powerconsumption is demonstrated by simulating the optimizeddecoders with real video streams.