VLSI array processors
Low-power architectural design methodologies
Low-power architectural design methodologies
System-Level Power Optimization of Video Codecs on Embedded Cores: A Systematic Approach
Journal of VLSI Signal Processing Systems - Special issue on future directions in the design and implementations of DSP systems
Formalized methodology for data reuse exploration for low-power hierarchical memory mappings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Strategy for power-efficient design of parallel systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Image and Video Compression Standards: Algorithms and Architectures
Image and Video Compression Standards: Algorithms and Architectures
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
Low Power Digital CMOS Design
Hierarchical algorithm partitioning at system level for an improved utilization of memory structures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Journal of Real-Time Image Processing
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Exploitation of data re-use in combination with the use of custom memory hierarchy that exploits the temporal locality of data accesses may introduce significant power savings, especially for data-intensive applications. The effect of the data-reuse decisions on the power dissipation but also on area and performance of multimedia applications realized on multiple embedded cores is explored. The interaction between the data-reuse decisions and the selection of a certain data-memory architecture model is also studied. As demonstrator a widely-used video processing algorithmic kernel, namely the full search motion estimation kernel, is used. Experimental results prove that improvements in both power and performance can be acquired, when the right combination of data memory architecture model and data-reuse transformation is selected.