Design of Processor Arrays for Reconfigurable Architectures
The Journal of Supercomputing
Exact Partitioning of Affine Dependence Algorithms
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Exact partitioning of affine dependence algorithms
Embedded processor design challenges
Optimization of Reconfiguration Overhead by Algorithmic Transformations and Hardware Matching
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Efficient control generation for mapping nested loop programs onto processor arrays
Journal of Systems Architecture: the EUROMICRO Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Controller synthesis for mapping partitioned programs on array architectures
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
Automatic FIR filter generation for FPGAs
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Automated Mapping of the MapReduce Pattern onto Parallel Computing Platforms
Journal of Signal Processing Systems
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The object of algorithm design in context with a hierarchically structured memory system is a reduction of access cycles to higher memory levels by an increase of data reuse from levels closer to execution units. The object of our approach is to systematically construct an algorithm coding, starting from a weak single assignment form, so that parameters of the algorithm code (number and type of partitions, scheduling orders) can be directly mapped on parameters of the architecture (number of memory levels, size of the memories, input/output access behavior) and vice versa. Target architectures are processors with from one up to a few execution units and with a hierarchically structured memory system. The approach is based on methods derived from the realm of array synthesis and consists of a recursively defined algorithm partitioning. An approach to a quantitative determination of data reuse in recursively partitioned algorithms is given