Automatic FIR filter generation for FPGAs

Authors:
Holger Ruckdeschel;Hritam Dutta;Frank Hannig;Jürgen Teich
Affiliations:
Department of Computer Science 12, Hardware-Software-Co-Design, University of Erlangen-Nuremberg, Germany;Department of Computer Science 12, Hardware-Software-Co-Design, University of Erlangen-Nuremberg, Germany;Department of Computer Science 12, Hardware-Software-Co-Design, University of Erlangen-Nuremberg, Germany;Department of Computer Science 12, Hardware-Software-Co-Design, University of Erlangen-Nuremberg, Germany
Venue:
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Year:
2005

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Abstract

This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. PARO is a design system project for modeling, transformation, optimization, and synthesis of massively parallel VLSI architectures. The FIR filter generator employs during the design flow the following advanced transformations, (a) hierarchical partitioning in order to balance the amount of local memory with external communication, and (b), partial localization to achieve higher throughput and smaller latencies. Furthermore, our filter generator allows for design space exploration to tackle trade-offs in cost and speed. Finally, synthesizable VHDL code is generated and mapped to an FPGA, the results are compared with a commercial filter generator.