PARO: Synthesis of Hardware Accelerators for Multi-dimensional Dataflow-Intensive Applications

Authors:
Frank Hannig;Holger Ruckdeschel;Hritam Dutta;Jürgen Teich
Affiliations:
Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany;Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany;Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany;Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
Venue:
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Year:
2008

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Abstract

In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications. Key features of PARO are: (1) The design entry in form of a compact and intuitive functional programming language which allows highly parallel implementations. (2) Advanced partitioning techniques are applied in order to balance the trade-offs in cost and performance along with requisite throughputs. This is obtained by distributing computations onto an array of tightly coupled processor elements. (3) We demonstrate the performance of the FPGA synthesized hardware with several selected algorithms from different benchmarks.