IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Recent advances in direct methods for solving unsymmetric sparse systems of linear equations
ACM Transactions on Mathematical Software (TOMS)
Strategies for Dynamic Load Balancing on Highly Parallel Computers
IEEE Transactions on Parallel and Distributed Systems
Efficient Run-Time Support for Irregular Task Computations with Mixed Granularities
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Preliminary Evaluation of Dynamic Load Balancing Using Loop Re-partitioning on Omni/SCASH
CCGRID '03 Proceedings of the 3st International Symposium on Cluster Computing and the Grid
Stream-Oriented FPGA Computing in the Streams-C High Level Language
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Xtensa with User Defined DSP Coprocessor Microarchitectures
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Automatic compilation to a coarse-grained reconfigurable system-opn-chip
ACM Transactions on Embedded Computing Systems (TECS)
An optimal algorithm for minimizing run-time reconfiguration delay
ACM Transactions on Embedded Computing Systems (TECS)
Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling
ACM Transactions on Embedded Computing Systems (TECS)
From application descriptions to hardware in seconds: a logic-based approach to bridging the gap
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An automated exploration framework for FPGA-based soft multiprocessor systems
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Optimal Free-Space Management and Routing-Conscious Dynamic Placement for Reconfigurable Devices
IEEE Transactions on Computers
Floating-to-fixed-point conversion for digital signal processors
EURASIP Journal on Applied Signal Processing
High-Performance Designs for Linear Algebra Operations on Reconfigurable Hardware
IEEE Transactions on Computers
Benchmarking GPUs to tune dense linear algebra
Proceedings of the 2008 ACM/IEEE conference on Supercomputing
PARO: Synthesis of Hardware Accelerators for Multi-dimensional Dataflow-Intensive Applications
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
Operating System for Symmetric Multiprocessors on FPGA
RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
Mapping the LU decomposition on a many-core architecture: challenges and solutions
Proceedings of the 6th ACM conference on Computing frontiers
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Floating-point FPGA: architecture and modeling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Overview of FPGA-Based Multiprocessor Systems
RECONFIG '09 Proceedings of the 2009 International Conference on Reconfigurable Computing and FPGAs
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Systems Architecture: the EUROMICRO Journal
A survey of hard real-time scheduling for multiprocessor systems
ACM Computing Surveys (CSUR)
Operating system for runtime reconfigurable multiprocessor systems
International Journal of Reconfigurable Computing - Special issue on selected papers from the 17th reconfigurable architectures workshop (RAW2010)
A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture
IPDPSW '11 Proceedings of the 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and PhD Forum
Hardware OS Communication Service and Dynamic Memory Management for RSoCs
RECONFIG '11 Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs
A performance and energy comparison of FPGAs, GPUs, and multicores for sliding-window applications
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
IEEE Transactions on Computers
DDBDD: Delay-Driven BDD Synthesis for FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-Level Synthesis for FPGAs: From Prototyping to Deployment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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State-of-the-art field-programmable gate array (FPGA) technologies have provided exciting opportunities to develop more flexible, less expensive, and better performance floating-point computing platforms for embedded systems. To better harness the full power of FPGAs and to bring FPGAs to more system designers, we investigate unique advantages and optimization opportunities in both software and hardware offered by multi-core processors on a programmable chip (MPoPCs). In this paper, we present our hardware customization and software dynamic scheduling solutions for LU factorization of large sparse matrices on in-house developed MPoPCs. Theoretical analysis is provided to guide the design. Implementation results on an Altera Stratix III FPGA for five benchmark matrices of size up to 7,917 脳 7,917 are presented. Our hardware customization alone can reduce the execution time by up to 17.22 %. The integrated hardware---software optimization improves the speedup by an average of 60.30 %.