Reconfigurable computing: a survey of systems and software

Authors:
Katherine Compton;Scott Hauck
Affiliations:
Northwestern University;University of Washington
Venue:
ACM Computing Surveys (CSUR)
Year:
2002

Citing 131
Cited 199

VLSI cell placement techniques

ACM Computing Surveys (CSUR)
Field-programmable gate arrays

Field-programmable gate arrays
Splash 2

SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
A high-performance microarchitecture with hardware-programmable functional units

MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
TIERS: Topology independent pipelined routing and scheduling for VirtualWire compilation

FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
PathFinder: a negotiation-based performance-driven router for FPGAs

FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
DPGA utilization and application

Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Sequencing run-time reconfigured hardware with software

Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Programmable active memories: reconfigurable systems come of age

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-FPGA systems

Multi-FPGA systems
A simulation tool for dynamically reconfigurable field programmable gate arrays

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 1995 IEEE ASIC conference
Board-level multiterminal net routing for FPGA-based logic emulation

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hierarchical interconnection structures for field programmable gate arrays

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture issues and solutions for a high-capacity FPGA

FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
I/O and performance tradeoffs with the FunctionBus during multi-FPGA partitioning

FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
General modeling and technology-mapping technique for LUT-based FPGAs

FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
The Transmogrifier-2: a 1 million gate rapid prototyping system

FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Improving functional density through run-time constant propagation

FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Synthesis and floorplanning for large hierarchical FPGAs

FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Performance driven floorplanning for FPGA based designs

FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
FPGA routing and routability estimation via Boolean satisfiability

FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
More wires and fewer LUTs: a design methodology for FPGAs

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Boolean matching for complex PLBs in LUT-based FPGAs with application to architecture evaluation

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
A new retiming-based technology mapping algorithm for LUT-based FPGAs

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
A hybrid complete-graph partial-crossbar routing architecture for multi-FPGA systems

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Managing pipeline-reconfigurable FPGAs

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Configuration prefetch for single context reconfigurable coprocessors

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Timing driven floorplanning on programmable hierarchical targets

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Fast module mapping and placement for datapaths in FPGAs

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Fast integrated tools for circuit design with FPGAs

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
A fast routability-driven router for FPGAs

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Scheduling designs into a time-multiplexed FPGA

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Partitioning sequential circuits on dynamically reconfiguable FPGAs

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
SMAP: heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Technology mapping for FPGAs with embedded memory blocks

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Hybrid product term and LUT based architectures using embedded memory blocks

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Cut ranking and pruning: enabling a general and efficient FPGA mapping solution

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
A methodology for fast FPGA floorplanning

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
FPGA routing architecture: segmentation and buffering to optimize speed and density

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really want 100% LUT utilization)

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Don't Care discovery for FPGA configuration compression

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
HSRA: high-speed, hierarchical synchronous reconfigurable array

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
A reconfigurable arithmetic array for multimedia applications

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Memory interfacing and instruction specification for reconfigurable processors

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Trading quality for compile time: ultra-fast placement for FPGAs

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Satisfiability-based layout revisited: detailed routing of complex FPGAs via search-based Boolean SAT

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Multi-terminal net routing for partial crossbar-based multi-FPGA systems

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Circuit partitioning for dynamically reconfigurable FPGAs

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Fast compilation for pipelined reconfigurable fabrics

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Configuration caching vs data caching for striped FPGAs

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers

IEEE Transactions on Computers
Dynamic Reconfiguration to Support Concurrent Applications

IEEE Transactions on Computers
The design of an SRAM-based field-programmable gate array—part I: architecture

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The design of a SRAM-based field-programmable gate array—part II: circuit design and layout

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An FPGA implementation and performance evaluation of the Serpent block cipher

FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Factoring large numbers with programmable hardware

FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
A reconfigurable multi-function computing cache architecture

FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
A representation for dynamic graphs in reconfigurable hardware and its application to fundamental graph algorithms

FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Hardware-software co-design of embedded reconfigurable architectures

Proceedings of the 37th Annual Design Automation Conference
Configuration compression for FPGA-based embedded systems

FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Configuration relocation and defragmentation for run-time reconfigurable computing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Seeking Solutions in Configurable Computing

Computer
The Garp Architecture and C Compiler

Computer
PipeRench: A Reconfigurable Architecture and Compiler

Computer
Routing Architectures for Hierarchical Field Programmable Gate Arrays

ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
A case study of partially evaluated hardware circuits: Key-specific DES

FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Technology mapping of LUT based FPGAs for delay optimisation

FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Technology mapping of heterogeneous LUT-based FPGAs

FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Run-time compaction of FPGA designs

FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
A hardware/software partitioning algorithm for custom computing machines

FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Run-time parameterised circuits for the Xilinx XC6200

FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
VPR: A new packing, placement and routing tool for FPGA research

FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
An operating system for custom computing machines based on the Xputer paradigm

FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Exploiting reconfigurability through domain-specific systems

FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Automatic mapping of algorithms onto multiple FPGA-SRAM modules

FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Pipeline morphing and virtual pipelines

FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
A Universal CLA Adder Generator for SRAM-Based FPGAs

FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Growable FPGA Macro Generator

FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
The Trianus System and Its Application to Custom Computing

FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
A New FPGA Technology Mapping Approach by Cluster Merging

FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
RaPiD - Reconfigurable Pipelined Datapath

FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Automated field-programmable compute accelerator design using partial evaluation

FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Acceleration of an FPGA router

FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
The Chimaera reconfigurable functional unit

FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A time-multiplexed FPGA

FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Garp: a MIPS processor with a reconfigurable coprocessor

FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A dynamic reconfiguration run-time system

FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Compilation tools for run-time reconfigurable designs

FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Automated target recognition on SPLASH 2

FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure

FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Accelerating Boolean Satisfiability with Configurable Hardware

FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
PAM-Blox: High Performance FPGA Design for Adaptive Computing

FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Object Oriented Circuit-Generators in Java

FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
JHDL - An HDL for Reconfigurable Systems

FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Specifying and Compiling Applications for RaPiD

FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
NAPA C: Compiling for a Hybrid RISC/FPGA Architecture

FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
The Design and Implementation of a Context Switching FPGA

FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Automating Production of Run-Time Reconfigurable Designs

FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Configuration Compression for the Xilinx XC6200 FPGA

FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Exploring Optimal Cost-Performance Designs for Raw Microprocessors

FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
The NAPA Adaptive Processing Architecture

FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications

FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Architecture and Design of GE1, a FCCM for Golomb Ruler Derivation

FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Debugging Techniques for Dynamically Reconfigurable Hardware

FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
CPR: A Configuration Profiling Tool

FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Improving Simulation Accuracy in Design Methodologies for Dynamically Reconfigurable Logic Systems

FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Runlength Compression Techniques for FPGA Configurations

FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator

FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A CAD Suite for High-Performance FPGA Design

FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Macro-Based Hardware Compilation of Java(tm) Bytecodes into a Dynamic Reconfigurable Computing System

FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
PCI-PipeRench and the SWORDAPI: A System for Stream-Based Reconfigurable Computing

FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor

FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Pipeline Vectorization for Reconfigurable Systems

FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Parallelizing Applications into Silicon

FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Automatic Allocation of Arrays to Memories in FPGA Processors with Multiple Memory Banks

FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
FPGA Implementation of a Microcoded Elliptic Curve Cryptographic Processor

FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Hardware-Software Codesign and Parallel Implementation of a Golomb Ruler Derivation Engine

FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Configuration Caching Management Techniques for Reconfigurable Computing

FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
A Reliable LZ Data Compressor on Reconfigurable Coprocessors

FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
A dynamic instruction set computer

FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
The Transmogrifier C hardware description language and compiler for FPGAs

FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Mesh routing topologies for multi-FPGA systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
New performance-driven FPGA routing algorithms

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Algorithms for an FPGA switch module routing problem with application to global routing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A performance and routability-driven router for FPGAs considering path delays

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Routing for array-type FPGA's

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pin assignment for multi-FPGA systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using cone structures for circuit partitioning into FPGA packages

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient algorithm for performance-optimal FPGA technology mapping with retiming

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Datapath merging and interconnection sharing for reconfigurable architectures

Proceedings of the 15th international symposium on System Synthesis
Configuration relocation and defragmentation for run-time reconfigurable computing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computing technology: frontiers and beyond

Engineering computational technology
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns

HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
A design methodology for NOC-based systems

Networks on chip
Performance of reconfigurable architectures for image-processing applications

Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
Run-time support for dynamically reconfigurable computing systems

Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
Special report: go reconfigure

IEEE Spectrum
Configuration-Sensitive Process Scheduling for FPGA-Based Computing Platforms

Proceedings of the conference on Design, automation and test in Europe - Volume 1
Designing multiple simultaneous seeds for DNA similarity search

RECOMB '04 Proceedings of the eighth annual international conference on Resaerch in computational molecular biology
Reconfigurable platforms for ubiquitous computing

Proceedings of the 1st conference on Computing frontiers
Adaptation of a low cost motion recognition system for custom operation from shrink-wrapped hardware

WBMA '03 Proceedings of the 2003 ACM SIGMM workshop on Biometrics methods and applications
An optimal algorithm for minimizing run-time reconfiguration delay

ACM Transactions on Embedded Computing Systems (TECS)
Field programmable gate arrays implementation of automated sensor self-validation system for cupola furnaces

Computers and Industrial Engineering
From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or Speculation

Proceedings of the 31st annual international symposium on Computer architecture
Security on FPGAs: State-of-the-art implementations and attacks

ACM Transactions on Embedded Computing Systems (TECS)
Evolvable computing by means of evolvable components

Natural Computing: an international journal
Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
The MOLEN Polymorphic Processor

IEEE Transactions on Computers
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip

IEEE Transactions on Parallel and Distributed Systems
Instruction set extension with shadow registers for configurable processors

Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
A Coprocessor for Accelerating Visual Information Processing

Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey

Journal of VLSI Signal Processing Systems
Reliability-Conscious Process Scheduling under Performance Constraints in FPGA-Based Embedded Systems

IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Reconfigurable Sequential Consistency Algorithm

IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Configuring the Circuit Switched Tree for Multiple Width Communications

IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 8 - Volume 09
CODACS Prototype: A Platform-Processor for CHIARA Programs

IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 13 - Volume 14
Reconfigurable universal SAD-multiplier array

Proceedings of the 2nd conference on Computing frontiers
Automatic generation of application-specific systems based on a micro-programmed Java core

Proceedings of the 2005 ACM symposium on Applied computing
Agent technology and reconfigurable computing for mobile devices

Proceedings of the 2005 ACM symposium on Applied computing
Hand tracking for low powered mobile AR user interfaces

AUIC '05 Proceedings of the Sixth Australasian conference on User interface - Volume 40
High-level synthesis for large bit-width multipliers on FPGAs: a case study

CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Hyperreconfigurable architectures and the partition into hypercontexts problem

Journal of Parallel and Distributed Computing
A novel reconfigurable hardware architecture for IP address lookup

Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
A Design Methodology for Efficient Application-Specific On-Chip Interconnects

IEEE Transactions on Parallel and Distributed Systems
Fracture Analysis Using Reconfigurable Computing Systems

HPCASIA '05 Proceedings of the Eighth International Conference on High-Performance Computing in Asia-Pacific Region
A Reconfigurable MPI Broadcast Function

HPCASIA '05 Proceedings of the Eighth International Conference on High-Performance Computing in Asia-Pacific Region
Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Optimal reconfiguration sequence management

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Run-time reconfigurable systems for digital signal processing applications: a survey

Journal of VLSI Signal Processing Systems
A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machines

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Event-oriented computing with reconfigurable platform

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Subtractive and Divisive Inhibition: Effect of Voltage-Dependent Inhibitory Conductances and Noise

Neural Computation
A new approach to compress the configuration information of programmable devices

Proceedings of the conference on Design, automation and test in Europe: Designers' forum
An EDF schedulability test for periodic tasks on reconfigurable hardware devices

Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Area and delay estimation for FPGA implementation of coarse-grained reconfigurable architectures

Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Verifying the adaptation behavior of embedded systems

Proceedings of the 2006 international workshop on Self-adaptation and self-managing systems
An object-oriented cryptosystem based on two-level reconfigurable computing architecture

Journal of Systems and Software
Reconfigurable Coprocessor for Multimedia Application Domain

Journal of VLSI Signal Processing Systems
Mapping of image processing systems to FPGA computer based on temporal partitioning and design space exploration

SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Stigmergic approaches applied to flexible fault-tolerant digital VLSI architectures

Journal of Parallel and Distributed Computing - Special issue on parallel bioinspired algorithms
A framework for mapping scalable networked applications on run-time reconfigurable platforms

ICME '03 Proceedings of the 2003 International Conference on Multimedia and Expo - Volume 2
The datapath merging problem in reconfigurable systems: Complexity, dual bounds and heuristic evaluation

Journal of Experimental Algorithmics (JEA)
A two-level reconfigurable architecture for digital signal processing

Microelectronic Engineering
Mapping data-parallel tasks onto partially reconfigurable hybrid processor architectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new decompression system for the configuration process of SRAM-based FPGAS

Proceedings of the 17th ACM Great Lakes symposium on VLSI
Low-power tradeoffs for mobile computing applications: embedded processors versus custom computing kernels

ACM-SE 45 Proceedings of the 45th annual southeast regional conference
Memory power optimization of hardware implementations of multimedia applications onto FPGA platforms

Journal of Embedded Computing - Low-power Embedded Systems
Reconfiguration in network of embedded systems: Challenges and adaptive tracking case study

Journal of Embedded Computing - Real-Time and Embedded Computing Systems
A hardware Memetic accelerator for VLSI circuit partitioning

Computers and Electrical Engineering
Low power data processing system with self-reconfigurable architecture

Journal of Systems Architecture: the EUROMICRO Journal
Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs

Journal of Systems Architecture: the EUROMICRO Journal
Automatic Design of Area-Efficient Configurable ASIC Cores

IEEE Transactions on Computers
Interactive presentation: A shift register based clause evaluator for reconfigurable SAT solver

Proceedings of the conference on Design, automation and test in Europe
Two-level microprocessor-accelerator partitioning

Proceedings of the conference on Design, automation and test in Europe
Didactic architectures and simulator for network processor learning

WCAE '03 Proceedings of the 2003 workshop on Computer architecture education: Held in conjunction with the 30th International Symposium on Computer Architecture
Teaching embedded systems with FPGAs throughout a computer science course

WCAE '04 Proceedings of the 2004 workshop on Computer architecture education: held in conjunction with the 31st International Symposium on Computer Architecture
RISPP: rotating instruction set processing platform

Proceedings of the 44th annual Design Automation Conference
Static scheduling techniques for dependent tasks on dynamically reconfigurable devices

Journal of Systems Architecture: the EUROMICRO Journal
Using simulated partial dynamic run-time reconfiguration to share embedded FPGA compute and power resources across a swarm of unpiloted airborne vehicles

EURASIP Journal on Embedded Systems
Examining the viability of FPGA supercomputing

EURASIP Journal on Embedded Systems
An overview of reconfigurable hardware in embedded systems

EURASIP Journal on Embedded Systems
A General Reconfigurable Architecture for the BLAST Algorithm

Journal of VLSI Signal Processing Systems
Resampling algorithms for particle filters: a computational complexity perspective

EURASIP Journal on Applied Signal Processing
Mapping streaming architectures on reconfigurable platforms

ACM SIGARCH Computer Architecture News - Special issue on the 2006 reconfigurable and adaptive architecture workshop
Architectural contesting: exposing and exploiting temperamental behavior

ACM SIGARCH Computer Architecture News - Special issue on the 2006 reconfigurable and adaptive architecture workshop
ReChannel: Describing and simulating reconfigurable hardware in systemC

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Self-Reconfigurable Embedded Systems on Low-Cost FPGAs

IEEE Micro
Real-Time Management of Hardware and Software Tasks for FPGA-based Embedded Systems

IEEE Transactions on Computers
Sharing of SRAM tables among NPN-equivalent LUTs in SRAM-based FPGAs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Allocation heuristics and defragmentation measures for reconfigurable systems management

Integration, the VLSI Journal
Multigrid solvers in reconfigurable hardware

Journal of Computational and Applied Mathematics
Modeling and simulation of parallel adaptive divide-and-conquer algorithms

The Journal of Supercomputing
Modelling Adaptive Systems in ForSyDe

Electronic Notes in Theoretical Computer Science (ENTCS)
Regular Expression Matching in Reconfigurable Hardware

Journal of Signal Processing Systems
A field programmable gate array media player for realmedia files

Journal of Computing Sciences in Colleges
Supporting tasks with adaptive groups in data parallel programming

International Journal of Computational Science and Engineering
Reconfigurable solutions for very-long arithmetic with applications in cryptography

Proceedings of the 18th ACM Great Lakes symposium on VLSI
Efficient controller implementations for robot control

CSECS'06 Proceedings of the 5th WSEAS International Conference on Circuits, Systems, Electronics, Control & Signal Processing
Dynamic image filter selection using partially reconfigurable FPGAs for imaging operations

CSECS'06 Proceedings of the 5th WSEAS International Conference on Circuits, Systems, Electronics, Control & Signal Processing
Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors

ACM Transactions on Embedded Computing Systems (TECS)
A fast IP routing lookup architecture for multi-gigabit switching routers based on reconfigurable systems

Microprocessors & Microsystems
Run-time instruction set selection in a transmutable embedded processor

Proceedings of the 45th annual Design Automation Conference
Perfecto: A systemc-based design-space exploration framework for dynamically reconfigurable architectures

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A compiler approach to managing storage and memory bandwidth in configurable architectures

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Performance and accuracy of hardware-oriented native-, emulated-and mixed-precision solvers in FEM simulations

International Journal of Parallel, Emergent and Distributed Systems
Run-time system for an extensible embedded processor with dynamic instruction set

Proceedings of the conference on Design, automation and test in Europe
Transparent reconfigurable acceleration for heterogeneous embedded applications

Proceedings of the conference on Design, automation and test in Europe
Run-Time Adaptable Architectures for Heterogeneous Behavior Embedded Systems

ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
A New Self-managing Hardware Design Approach for FPGA-Based Reconfigurable Systems

ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Using GPUs to improve multigrid solver performance on a cluster

International Journal of Computational Science and Engineering
Automatic design of reconfigurable domain-specific flexible cores

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Rapid design of area-efficient custom instructions for reconfigurable embedded processing

Journal of Systems Architecture: the EUROMICRO Journal
Engineering of Software-Intensive Systems: State of the Art and Research Challenges

Software-Intensive Systems and New Computing Paradigms
Synthesis of reconfigurable high-performance multicore systems

Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
The input-aware dynamic adaptation of area and performance for reconfigurable accelerator

Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
An application-centered design flow for self reconfigurable systems implementation

Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Temporal Partitioning to Amortize Reconfiguration Overhead for Dynamically Reconfigurable Architectures

IEICE - Transactions on Information and Systems
A Model of Computation for Bit-Level Concurrent Computing and Programming: APEC

IEICE - Transactions on Information and Systems
Implementation of parallel edit distance algorithm for protein sequences using reconfigurable accelerator

Proceedings of the International Conference on Advances in Computing, Communication and Control
Agility index of automatic production systems: Reconfigurable logic and open source as agility enablers

Computers in Industry
Ultra-Fast Downloading of Partial Bitstreams through Ethernet

ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
Parametric Design for Reconfigurable Software-Defined Radio

ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep

ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing

Microprocessors & Microsystems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths

Integration, the VLSI Journal
Reconfigurable Multithreading Architectures: A Survey

SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
A Performance Model for Run-Time Reconfigurable Hardware Accelerator

APPT '09 Proceedings of the 8th International Symposium on Advanced Parallel Processing Technologies
An embedded and programmable system based FPGA for real time, MPEG stream buffer analysis

IEEE Transactions on Circuits and Systems for Video Technology
Hardware accelerated FPGA placement

Microelectronics Journal
A framework for core-level modeling and design of reconfigurable computing algorithms

Proceedings of the Third International Workshop on High-Performance Reconfigurable Computing Technology and Applications
Processor-efficient sparse matrix-vector multiplication

Computers & Mathematics with Applications
REMiS: run-time energy minimization scheme in a reconfigurable processor with dynamic power-gated instruction set

Proceedings of the 2009 International Conference on Computer-Aided Design
ReSP: a nonintrusive transaction-level reflective MPSoC simulation platform for design space exploration

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks

Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Compiling for reconfigurable computing: A survey

ACM Computing Surveys (CSUR)
Security Primitives for Reconfigurable Hardware-Based Systems

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Algorithmic skeletons for the programming of reconfigurable systems

SEUS'07 Proceedings of the 5th IFIP WG 10.2 international conference on Software technologies for embedded and ubiquitous systems
Dynamic replacement of video coding elements

Image Communication
Design of a simulator for mesh-based reconfigurable architectures

NPC'07 Proceedings of the 2007 IFIP international conference on Network and parallel computing
Improving flexibility in on-line evolvable systems by reconfigurable computing

ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
Software development for a novel WSN platform

Proceedings of the 2010 ICSE Workshop on Software Engineering for Sensor Network Applications
Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Characterization of Fixed and Reconfigurable Multi-Core Devices for Application Acceleration

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
FPGA-Array with Bandwidth-Reduction Mechanism for Scalable and Power-Efficient Numerical Simulations Based on Finite Difference Methods

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
FPGA based real-time image segmentation for medical systems and data processing

RTC'05 Proceedings of the 14th IEEE-NPSS conference on Real time
Demonstration of an in-band reconfiguration data distribution and network node reconfiguration

Proceedings of the Conference on Design, Automation and Test in Europe
Toward a runtime system for reconfigurable computers: a virtualization approach

Proceedings of the Conference on Design, Automation and Test in Europe
Efficient task scheduling for runtime reconfigurable systems

Journal of Systems Architecture: the EUROMICRO Journal
High-level synthesis with reconfigurable datapath components

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Dynamically reconfigurable cache architecture using adaptive block allocation policy

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
FPGA implementation of a license plate recognition SoC using automatically generated streaming accelerators

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Partitioned scheduling of periodic real-time tasks onto reconfigurable hardware

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Exploiting processing locality through paging configurations in multitasked reconfigurable systems

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Coupling of a reconfigurable architecture and a multithreaded processor core with integrated real-time scheduling

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Binary acceleration using coarse-grained reconfigurable architecture

ACM SIGARCH Computer Architecture News
FPGA implementation of the pixel purity index algorithm for remotely sensed hyperspectral image analysis

EURASIP Journal on Advances in Signal Processing
Performance estimation framework for automated exploration of CPU-accelerator architectures

Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Collaboration of reconfigurable processors in grid computing: Theory and application

Future Generation Computer Systems
The Instruction-Set Extension Problem: A Survey

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Scientific Application Demands on a Reconfigurable Functional Unit Interface

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
CReAMS: an embedded multiprocessor platform

ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
On the design of a hardware-software architecture for acceleration of SVM's training phase

MCPR'10 Proceedings of the 2nd Mexican conference on Pattern recognition: Advances in pattern recognition
Boosting parallel applications performance on applying DIM technique in a multiprocessing environment

International Journal of Reconfigurable Computing - Special issue on selected papers from the 17th reconfigurable architectures workshop (RAW2010)
High performance and area efficient flexible DSP datapath synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Algorithms and hardware architectures for variable block size motion estimation

UIC'11 Proceedings of the 8th international conference on Ubiquitous intelligence and computing
RCMP: a reconfigurable chip-multiprocessor architecture

ISPA'06 Proceedings of the 2006 international conference on Frontiers of High Performance Computing and Networking
Parallel image segmentation in reconfigurable chip multiprocessors

ISPA'06 Proceedings of the 2006 international conference on Frontiers of High Performance Computing and Networking
Efficient datapath merging for the overhead reduction of run-time reconfigurable systems

The Journal of Supercomputing
Stochastic allocation and scheduling for conditional task graphs in MPSoCs

CP'06 Proceedings of the 12th international conference on Principles and Practice of Constraint Programming
Context-Aware negotiation for reconfigurable resources with handheld devices

OTM'05 Proceedings of the 2005 OTM Confederated international conference on On the Move to Meaningful Internet Systems
Performance and power evaluation of an intelligently adaptive data cache

HiPC'05 Proceedings of the 12th international conference on High Performance Computing
UML-Based design flow and partitioning methodology for dynamically reconfigurable computing systems

EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
Reconfigurable gang scheduling algorithm

JSSPP'04 Proceedings of the 10th international conference on Job Scheduling Strategies for Parallel Processing
CODACS project: a development tool for embedded system prototyping

ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
Other issues

Embedded Systems Design
Computing platforms

Embedded Systems Design
A tutorial on physical security and side-channel attacks

Foundations of Security Analysis and Design III
FPGA based accelerator for 3-SAT conflict analysis in SAT solvers

CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
LARA: an aspect-oriented programming language for embedded systems

Proceedings of the 11th annual international conference on Aspect-oriented Software Development
DRIL– a flexible architecture for blowfish encryption using dynamic reconfiguration, replication, inner-loop pipelining, loop folding techniques

ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Policy-driven memory protection for reconfigurable hardware

ESORICS'06 Proceedings of the 11th European conference on Research in Computer Security
Optimization of Shared High-Performance Reconfigurable Computing Resources

ACM Transactions on Embedded Computing Systems (TECS)
Improving performance of adaptive component-based dataflow middleware

Parallel Computing
Evaluation of runtime task mapping using the rSesame framework

International Journal of Reconfigurable Computing - Special issue on Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
FPGA based efficient on-chip memory for image processing algorithms

Microelectronics Journal
On the Evolution of Hardware Circuits via Reconfigurable Architectures

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Dynamically reconfigurable entropy coder for multi-standard video adaptation using FaRM

Microprocessors & Microsystems
MORPHEUS: A heterogeneous dynamically reconfigurable platform for designing highly complex embedded systems

ACM Transactions on Embedded Computing Systems (TECS)
Towards a multiple-ISA embedded system

Journal of Systems Architecture: the EUROMICRO Journal
Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints

ACM Transactions on Architecture and Code Optimization (TACO)
Representing dynamic pluggable software units

Proceedings of the 28th Annual ACM Symposium on Applied Computing
Triggered instructions: a control paradigm for spatially-programmed architectures

Proceedings of the 40th Annual International Symposium on Computer Architecture
Playing games with scenario- and resource-aware SDF graphs through policy iteration

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Design space exploration for partially reconfigurable architectures in real-time systems

Journal of Systems Architecture: the EUROMICRO Journal
UNTANGLED: A Game Environment for Discovery of Creative Mapping Strategies

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Wheelchairs Embedded Control System Design for Secure Navigation with RF Signal Triangulation

Journal of Information Technology Research
Energy-efficient scheduling on multi-FPGA reconfigurable systems

Microprocessors & Microsystems
Ingredients of adaptability: a survey of reconfigurable processors

VLSI Design
ISOMER: integrated selection, partitioning, and placement methodology for reconfigurable architectures

Proceedings of the International Conference on Computer-Aided Design
Clustering scheduling for hardware tasks in reconfigurable computing systems

Journal of Systems Architecture: the EUROMICRO Journal
FPGA implementation of particle swarm optimization for Bayesian network learning

Computers and Electrical Engineering
The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms

Journal of Real-Time Image Processing
Hardware---software optimizations of reconfigurable multi-core processors for floating-point computations of large sparse matrices

Journal of Real-Time Image Processing
Energy and throughput aware fuzzy logic based reconfiguration for MPSoCs

Journal of Intelligent & Fuzzy Systems: Applications in Engineering and Technology

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Abstract

Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solution. In this survey, we explore the hardware aspects of reconfigurable computing machines, from single chip architectures to multi-chip systems, including internal structures and external coupling. We also focus on the software that targets these machines, such as compilation tools that map high-level algorithms directly to the reconfigurable substrate. Finally, we consider the issues involved in run-time reconfigurable systems, which reuse the configurable hardware during program execution.