Performance-driven system partitioning on multi-chip modules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Optimal clustering for delay minimization
DAC '93 Proceedings of the 30th international Design Automation Conference
Multiple FPGA partitioning with performance optimization
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Multi-way partitioning for minimum delay for look-up table based FPGAs
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Timing driven placement for large standard cell circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Timing influenced force directed floorplanning
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
A new system partitioning method under performance and physical constraints for multi-chip modules
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Partitioning with cone structures
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Timing influenced layout design
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Circuit clustering for delay minimization under area and pin constraints
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Timing-driven placement for hierarchical programmable logic devices
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Adaptive delay estimation for partitioning-driven PLD placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Multilevel optimization for large-scale hierarchical FPGA placement
Journal of Computer Science and Technology
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The goal of this paper is to perform a timing optimization of a circuit described b y a network of cells on a target structure whose connection delays ha v ediscrete values follo wing its hierarch y. The circuits is modelled by a set of timed cones whose delay histograms allow their classification into critical, potential critical and neutral cones according to predicted delays. The floorplanning is then guided b y this cone structuring and has two innov ativ e features:first, it is shown that the placement of the elements of the neutral cones has no impact on timing results, th us a significant reduction is obtained; second, despite a greedy approach, a near optimal floorplan is achieved in a large number of examples.