Partitioning with cone structures

Multiple FPGA partitioning with performance optimization

FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays

PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Combinational logic synthesis for LUT based field programmable gate arrays

ACM Transactions on Design Automation of Electronic Systems (TODAES)

A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Multi-way FPGA partitioning by fully exploiting design hierarchy

DAC '97 Proceedings of the 34th annual Design Automation Conference

Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy

ISPD '98 Proceedings of the 1998 international symposium on Physical design

Timing driven floorplanning on programmable hierarchical targets

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays

Iterative improvement based multi-way netlist partitioning for FPGAs

DATE '99 Proceedings of the conference on Design, automation and test in Europe

Multiway FPGA partitioning by fully exploiting design hierarchy

ACM Transactions on Design Automation of Electronic Systems (TODAES)

ASIC Prototyping with Reprogrammable Implementations of Large ASICs

RSP '96 Proceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)

A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation

Proceedings of the 21st International Workshop on Principles of Advanced and Distributed Simulation

A Multiway Design-driven Partitioning Algorithm for Distributed Verilog Simulation

Simulation