High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
An efficient method of partitioning circuits for multiple-FPGA implementation.
DAC '93 Proceedings of the 30th international Design Automation Conference
Cost minimization of partitions into multiple devices
DAC '93 Proceedings of the 30th international Design Automation Conference
DAC '94 Proceedings of the 31st annual Design Automation Conference
Circuit partitioning for huge logic emulation systems
DAC '94 Proceedings of the 31st annual Design Automation Conference
Spectral-based multi-way FPGA partitioning
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Multi-way system partitioning into a single type or multiple types of FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Multiple FPGA partitioning with performance optimization
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Multi-way partitioning for minimum delay for look-up table based FPGAs
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Partitioning with cone structures
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Optimal replication for min-cut partitioning
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Parallel placement for field-programmable gate arrays
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
An Efficient Logic Emulation System
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Design hierarchy guided multilevel circuit partitioning
Proceedings of the 2002 international symposium on Physical design
A genetic algorithm high-level optimizer for complex datapath and data-flow digital systems
Applied Soft Computing
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Intel nehalem processor core made FPGA synthesizable
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Multi-FPGA partitioning method based on topological levelization
Journal of Electrical and Computer Engineering
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In this paper, we present a new integrated synthesis and partitioning method for multiple-FPGA applications. Our approach bridges the gap between HDL synthesis and physical partitioning by fully exploiting the design hierarchy. We propose a novel multiple-FPGA synthesis and partitioning method which is performed in three phases: (1) fine-grained synthesis, (2) functional-based clustering, and (3) hierarchical set-covering partitioning. This method first synthesizes a design specification in a fine-grained way so that functional clusters can be preserved based on the structural nature of the design specification. Then, it applies a hierarchical set-covering partitioning method to form the final FPGA partitions. Experimental results on a number of benchmarks and industrial designs demonstrate that I&slash;O limits are the bottleneck for CLB utilization when applying a traditional multiple-FPGA synthesis method on flattened netlists. In contrast, by fully exploiting the design structural hierarchy during the multiple-FPGA partitioning, our proposed method produces fewer FPGA partitions with higher CLB and lower I&slash;O-pin utilizations.