Improving the performance of the Kernighan-Lin and simulated annealing graph bisection algorithms
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
An efficient method of partitioning circuits for multiple-FPGA implementation.
DAC '93 Proceedings of the 30th international Design Automation Conference
Cost minimization of partitions into multiple devices
DAC '93 Proceedings of the 30th international Design Automation Conference
Spectral K-way ratio-cut partitioning and clustering
DAC '93 Proceedings of the 30th international Design Automation Conference
The application of hierarchical trees to circuit partitioning, clock net routing, and connectivity verification problems
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
On the partitioning of graphs and hypergraphs
On the partitioning of graphs and hypergraphs
EURO-DAC '94 Proceedings of the conference on European design automation
Spectral-based multi-way FPGA partitioning
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Multi-way system partitioning into a single type or multiple types of FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
On optimal board-level routing for FPGA-based logic emulation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Board-level multi-terminal net routing for FPGA-based logic emulation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Board-level multiterminal net routing for FPGA-based logic emulation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Module generation of complex macros for logic-emulation applications
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Multi-way FPGA partitioning by fully exploiting design hierarchy
DAC '97 Proceedings of the 34th annual Design Automation Conference
A hierarchy-driven FPGA partitioning method
DAC '97 Proceedings of the 34th annual Design Automation Conference
Network flow based multi-way partitioning with area and pin constraints
Proceedings of the 1997 international symposium on Physical design
Circuit partitioning with complex resource constraints in FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Performance-driven multi-FPGA partitioning using functional clustering and replication
DAC '98 Proceedings of the 35th annual Design Automation Conference
On multilevel circuit partitioning
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Iterative improvement based multi-way netlist partitioning for FPGAs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Multiway FPGA partitioning by fully exploiting design hierarchy
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Board-level multiterminal net assignment
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Integrating HDL Synthesis and Partitioning for Multi-FPGA Designs
IEEE Design & Test
Board-level multiterminal net assignment for the partial cross-bar architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
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