Circuit partitioning for huge logic emulation systems
DAC '94 Proceedings of the 31st annual Design Automation Conference
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Hardware emulation for functional verification of K5
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Computer-Aided Prototyping for ASIC-Based Systems
IEEE Design & Test
Emulation verification of the Motorola 68060
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
An Efficient Logic Emulation System
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Preserving HDL synthesis hierarchy for cell placement
Proceedings of the 1997 international symposium on Physical design
Integrating HDL Synthesis and Partitioning for Multi-FPGA Designs
IEEE Design & Test
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Logic emulation is a technique that uses dynamically reprogrammable systems for prototyping and design verification. Using an emulator, designers can realize designs through a software configuration process and perform real-time design verification before fabricating the chip into silicon. However, converting designs into an emulator involves the use of multi-phase design tasks, which is a very time-consuming process. Hence, shortening the Time-To-Emulation (TTE) is always the main concern for the logic-emulation design process. One approach t o shorten the design processing time is to replace portions of the design with macro cells. This paper presents a module generator for logic-emulation applications, which is able to generate macro cells of arbitrarily complex functions described in High-level Descriptive Languages the (HDLs), Furthermore, the module generator can effectively generate a multiple-FPGA macro for large macros which can not fit in a single FPGA chip. Experiments using the module generator for logic emulation are reported. The results demonstrate that the module generator can effectively and efficiently generate complex macros from their Register-Transfer-Level (RTL) description. In addition, the results also show that the design processing time is significantly shortened when the module generation method is incorporated into the logic-emulation design flow.