Computer engineering hardware design
Computer engineering hardware design
An efficient method of partitioning circuits for multiple-FPGA implementation.
DAC '93 Proceedings of the 30th international Design Automation Conference
DAC '94 Proceedings of the 31st annual Design Automation Conference
Circuit partitioning for huge logic emulation systems
DAC '94 Proceedings of the 31st annual Design Automation Conference
Spectral-based multi-way FPGA partitioning
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Multi-way system partitioning into a single type or multiple types of FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Multiple FPGA partitioning with performance optimization
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Multi-way partitioning for minimum delay for look-up table based FPGAs
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Partitioning with cone structures
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Optimal replication for min-cut partitioning
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Computer-Aided Prototyping for ASIC-Based Systems
IEEE Design & Test
An Efficient Logic Emulation System
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Module generation of complex macros for logic-emulation applications
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multi-way FPGA partitioning by fully exploiting design hierarchy
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multiway FPGA partitioning by fully exploiting design hierarchy
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Integrating HDL Synthesis and Partitioning for Multi-FPGA Designs
IEEE Design & Test
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In this paper, we present a new synthesis and partitioning approach for multiple-FPGA implementations from Register-Transfer-Level (RTL) netlists. Our approach bridges the gap between RTL/logic synthesis and physical partitioning by finely tuning logic implementations suited for multiple-FPGA systems. We propose a hierarchical functional structuring and partitioning method which fully exploits the design structural hierarchy by decomposing RTL components into sets of logic sub-functions. This allows the partitioner to place portions of components into FPGA partitions. Experimental results on a number of benchmarks and industrial designs show that our approach achieves significant improvements in CLB and IO-pin utilizations of FPGAs compared to that produced using a traditional multiple-FPGA partitioning method.