Multi-way netlist partitioning into heterogeneous FPGAs and minimization of total device cost and interconnect

A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions

EURO-DAC '94 Proceedings of the conference on European design automation

Multi-way system partitioning into a single type or multiple types of FPGAs

FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays

Multi-way partitioning for minimum delay for look-up table based FPGAs

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Circuit partitioning with logic perturbation

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Hierarchical partitioning

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

A hierarchy-driven FPGA partitioning method

DAC '97 Proceedings of the 34th annual Design Automation Conference

Replication for logic bipartitioning

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Performance-driven multi-FPGA partitioning using functional clustering and replication

DAC '98 Proceedings of the 35th annual Design Automation Conference

On multilevel circuit partitioning

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

Iterative improvement based multi-way netlist partitioning for FPGAs

DATE '99 Proceedings of the conference on Design, automation and test in Europe

Multiway FPGA partitioning by fully exploiting design hierarchy

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Circuit partitioning with coupled logic restructuring techniques

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference

Min-cut partitioning with functional replication for technology mapped circuits using minimum area overhead

Proceedings of the 2001 international symposium on Physical design

Automated design synthesis and partitioning for adaptive reconfigurable hardware

Hardware implementation of intelligent systems

An evaluation of bipartitioning techniques

ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)

Hierarchical Partitioning in a Rapid Prototyping Environment

RSP '96 Proceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)

Further improve circuit partitioning using GBAW logic perturbation techniques

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)

Replicated partitioning for undirected hypergraphs

Journal of Parallel and Distributed Computing