Efficient algorithms for finding maximum matching in graphs
ACM Computing Surveys (CSUR)
A linear-time heuristic for improving network partitions
25 years of DAC Papers on Twenty-five years of electronic design automation
Improving the performance of the Kernighan-Lin and simulated annealing graph bisection algorithms
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Net partitions yield better module partitions
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A general purpose multiple way partitioning algorithm
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A probabilistic multicommodity-flow solution to circuit clustering problems
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
A parallel bottom-up clustering algorithm with applications to circuit partitioning in VLSI design
DAC '93 Proceedings of the 30th international Design Automation Conference
FPGA partitioning under timing constraints
Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs
Efficient network flow based min-cut balanced partitioning
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
DAC '94 Proceedings of the 31st annual Design Automation Conference
Partitioning very large circuits using analytical placement techniques
DAC '94 Proceedings of the 31st annual Design Automation Conference
EURO-DAC '94 Proceedings of the conference on European design automation
Logic partition orderings for multi-FPGA systems
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
A timing driven N-way chip and multi-chip partitioner
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Clustering and linear placement
DAC '72 Proceedings of the 9th Design Automation Workshop
An Improved Min-Cut Algonthm for Partitioning VLSI Networks
IEEE Transactions on Computers
Logic partition orderings for multi-FPGA systems
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
System partitioning to maximize sleep time
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Partitioning of VLSI circuits and systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multilevel circuit partitioning
DAC '97 Proceedings of the 34th annual Design Automation Conference
Replication for logic bipartitioning
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Hybrid spectral/iterative partitioning
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
On multilevel circuit partitioning
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Multilevel k-way hypergraph partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Multi-way partitioning using bi-partition heuristics
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Wavefront Diffusion and LMSR: Algorithms for Dynamic Repartitioning of Adaptive Meshes
IEEE Transactions on Parallel and Distributed Systems
Sourcebook of parallel computing
Multi.Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
On ATPG for multiple aggressor crosstalk faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilevel algorithms for partitioning power-law graphs
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Refining graph partitioning for social network clustering
WISE'10 Proceedings of the 11th international conference on Web information systems engineering
Exploiting small world property for network clustering
World Wide Web
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Logic partitioning is an important issue in VLSI CAD, and has been an active area of research for at least the last 25 years. Numerous approaches have been developed and many different techniques have been combined for a wide range of applications. In this paper, we examine many of the existing techniques for logic bipartitioning and present a methodology for determining the best mix of approaches. The result is a novel bipartitioning algorithm that includes both new and pre-existing techniques. Our algorithm produces results that are at least 17% better than the state-of-the-art while also being efficient in run time.