The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
Efficient placement and routing techniques for master slice LSI
DAC '80 Proceedings of the 17th Design Automation Conference
A proper model for the partitioning of electrical circuits
DAC '72 Proceedings of the 9th Design Automation Workshop
A class of min-cut placement algorithms
DAC '77 Proceedings of the 14th Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
A placement capability based on partitioning
DAC '79 Proceedings of the 16th Design Automation Conference
Constructing test cases for partitioning heuristics
IEEE Transactions on Computers
Combining Logic Minimization and Folding for PLAs
IEEE Transactions on Computers
Dynamic Iterative Method for Fast Network Partitioning
HPCN Europe 2000 Proceedings of the 8th International Conference on High-Performance Computing and Networking
Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning
ALENEX '99 Selected papers from the International Workshop on Algorithm Engineering and Experimentation
An evaluation of bipartitioning techniques
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
A new fuzzy-clustering-based approach for two-way circuit partitioning
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Multi-way partitioning of VLSI circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Geometric bipartitioning problem and its applications to VLSI
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
An Efficient Multi-Level Partitioning Algorithm for VLSI Circuits
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
An Evaluation of Move-Based Multi-Way Partitioning Algorithms
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Teramac-configurable custom computing
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Parallel multilevel algorithms for hypergraph partitioning
Journal of Parallel and Distributed Computing
Graph partitioning through a multi-objective evolutionary algorithm: a preliminary study
Proceedings of the 10th annual conference on Genetic and evolutionary computation
Application-specific networks-on-chip topology customization using network partitioning
IFMT '08 Proceedings of the 1st international forum on Next-generation multicore/manycore technologies
Partitioning and floor-planning for data-path chip (microprocessor) layout
Integration, the VLSI Journal
An efficient heuristic for standard-cell placement
Integration, the VLSI Journal
Evaluating the Kernighan-Lin Heuristic for Hardware/Software Partitioning
International Journal of Applied Mathematics and Computer Science
Multiple-counterexample guided iterative abstraction refinement: an industrial evaluation
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Genetic approaches for graph partitioning: a survey
Proceedings of the 13th annual conference on Genetic and evolutionary computation
Evaluating inlining techniques
Computer Languages
Netlist bipartitioning using particle swarm optimisation technique
International Journal of Artificial Intelligence and Soft Computing
| Hi-index | 14.99 |
Recently, a fast (linear) heuristic for improving min-cut partitions of VLSI networks was suggested by Fiduccia and Mattheyses [6]. In this-paper we generalize their ideas and suggest a class of increasingly sophisticated heuristics. We then show, by exploiting the data structures originally suggested by them, that the computational complexity of any specific heuristic in the suggested class remains linear in the size of the network.