Timing Analysis Using Functional Analysis
IEEE Transactions on Computers
Multiple-Way Network Partitioning
IEEE Transactions on Computers
Combinatorial algorithms for integrated circuit layout
Combinatorial algorithms for integrated circuit layout
Logical effort: designing for speed on the back of an envelope
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Timing driven placement using complete path delays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
An entropy measure for the complexity of multi-output Boolean functions
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Layout driven technology mapping
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Technology decomposition and mapping targeting low power dissipation
DAC '93 Proceedings of the 30th international Design Automation Conference
Surveys in combinatorics, 1993
Surveys in combinatorics, 1993
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Precomputation-based sequential logic optimization for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Low-power design techniques for high-performance CMOS adders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Minimizing the routing cost during logic extraction
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An algorithm for incremental timing analysis
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Activity-driven clock design for low power circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
System partitioning to maximize sleep time
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power vs. delay in gate sizing: conflicting objectives?
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
VLSI circuit partitioning by cluster-removal using iterative improvement techniques
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Embedded tutorial: speed: new paradigms in design for performance
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Physical design CAD in deep sub-micron era
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Two dimensional codes for low power
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Architecture and routability analysis for row-based FPGAs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A spacing algorithm for performance enhancement and cross-talk reduction
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
System-level power optimization of special purpose applications: the beach solution
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
A method of redundant clocking detection and power reduction at RT level design
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
A gate resizing technique for high reduction in power consumption
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Post-layout logic restructuring for performance optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
Layout driven re-synthesis for low power consumption LSIs
DAC '97 Proceedings of the 34th annual Design Automation Conference
NRG: global and detailed placement
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
An exact solution to simultaneous technology mapping and linear placement problem
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Timing driven placement in interaction with netlist transformations
Proceedings of the 1997 international symposium on Physical design
Proceedings of the 1997 international symposium on Physical design
The quarter micron challenge: intergrating physical and logic design
Proceedings of the 1997 international symposium on Physical design
Proceedings of the 1997 international symposium on Physical design
The future of logic synthesis and physical design in deep-submicron process geometries
Proceedings of the 1997 international symposium on Physical design
Layout-driven RTL binding techniques for high-level synthesis using accurate estimators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Energy minimization using multiple supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Gate sizing for constrained delay/power/area optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Analysis, reduction and avoidance of crosstalk on VLSI chips
ISPD '98 Proceedings of the 1998 international symposium on Physical design
IEEE Transactions on Computers
DAC '98 Proceedings of the 35th annual Design Automation Conference
A DSM design flow: putting floorplanning, technology-mapping, and gate-placement together
DAC '98 Proceedings of the 35th annual Design Automation Conference
A framework for estimation and minimizing energy dissipation of embedded HW/SW systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Potential-NRG: placement with incomplete data
DAC '98 Proceedings of the 35th annual Design Automation Conference
Global routing with crosstalk constraints
DAC '98 Proceedings of the 35th annual Design Automation Conference
Timing and crosstalk driven area routing
DAC '98 Proceedings of the 35th annual Design Automation Conference
FPGA routing and routability estimation via Boolean satisfiability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wireplanning in logic synthesis
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Gate-size selection for standard cell libraries
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A simultaneous routing tree construction and fanout optimization algorithm
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Fine grain incremental rescheduling via architectural retiming
Proceedings of the 11th international symposium on System synthesis
Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Dynamic Trees and Dynamic Point Location
SIAM Journal on Computing
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Interconnect coupling noise in CMOS VLSI circuits
ISPD '99 Proceedings of the 1999 international symposium on Physical design
On the behavior of congestion minimization during placement
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Crosstalk constrained global route embedding
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Common-case computation: a high-level technique for power and performance optimization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Crosstalk minimization using wire perturbations
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A low power hardware/software partitioning approach for core-based embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Multilevel k-way hypergraph partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Wave steering in YADDs: a novel non-iterative synthesis and layout technique
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Interconnect estimation and planning for deep submicron designs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Dynamic power management based on continuous-time Markov decision processes
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
TimberWolf3.2: a new standard cell placement and global routing package
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Provably good algorithm for low power consumption with dual supply voltages
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Towards true crosstalk noise analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Optimal P/N width ratio selection for standard cell libraries
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Integrated floorplanning and interconnect planning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Timing-safe false path removal for combinational modules
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
On the Power of Logic Resynthesis
SIAM Journal on Computing
Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
An Introduction to VLSI Physical Design
An Introduction to VLSI Physical Design
Bounded Incremental Computation
Bounded Incremental Computation
Saving Power by Synthesizing Gated Clocks for Sequential Circuits
IEEE Design & Test
Logic extraction based on normalized netlengths
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Incremental methods for FSM traversal
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
DART: delay and routability driven technology mapping for LUT based FPGAs
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Energy recovery for low-power CMOS
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Reducing Address Bus Transitions for Low Power Memory Mapping
EDTC '96 Proceedings of the 1996 European conference on Design and Test
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Prediction of wiring space requirements for LSI
DAC '77 Proceedings of the 14th Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
A fast algorithm to test planar topological routability
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
A Graph-Theoretic Approach for Register File Based Synthesis
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
An Improved Min-Cut Algonthm for Partitioning VLSI Networks
IEEE Transactions on Computers
A Formula for Logical Network Cost
IEEE Transactions on Computers
Dynamic half-space reporting, geometric optimization, and minimum spanning trees
SFCS '92 Proceedings of the 33rd Annual Symposium on Foundations of Computer Science
Sparsification-a technique for speeding up dynamic graph algorithms
SFCS '92 Proceedings of the 33rd Annual Symposium on Foundations of Computer Science
Logical Network Cost and Entropy
IEEE Transactions on Computers
Scheduling with multiple voltages
Integration, the VLSI Journal
Incremental layout placement modification algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Spectral-based multiway FPGA partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Postlayout logic restructuring using alternative wires
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing-driven placement for regular architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimum replication min-cut partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post global routing crosstalk synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sequential logic optimization for low power using input-disabling precomputation architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On crossing minimization problem
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance optimization by gate sizing and path sensitization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level power modeling, estimation, and optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Nostradamus: a floorplanner of uncertain designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level area and power estimation for VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Delay-optimal clustering targeting low-power VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Harmony: static noise analysis of deep submicron digital integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Evaluation and optimization of replication algorithms for logic bipartitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An integrated logical and physical design flow for deep submicron circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Min-cut replication in partitioned networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Functional timing analysis using ATPG
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Estimation and removal or routing congestion (discussion session)
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
A System for Automatic Recording and Prediction of Design Quality Metrics
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Efficient on-line module-level wake-up scheduling for high performance multi-module designs
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
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In this paper we survey major problems faced by EDA tools in tackling submicron (DSM) design challenges like: crosstalk, reliability, power, and interconnect dominated delay. We discuss the need for rethinking quality models used in EDA tools to allow early and reliable planning, estimation, analysis, and optimization. Key design quality metrics from a CAD tool perspective are surveyed, and methodologies and directions are proposed for the next generation design automation tools, intended to meet the challenges ahead. Ideas such as forward synthesis, incremental synthesis, system-level interconnect prediction and planning, and their implications on design quality, design tool architecture, and design methodology are explored.