DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Performance-oriented technology mapping
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Multilevel synthesis minimizing the routing factor
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Proud: a fast sea-of-gates placement algorithm
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Timing influenced layout design
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Optimal Code Generation for Expression Trees
Journal of the ACM (JACM)
A near optimal algorithm for technology mapping minimizing area under delay constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
EURO-DAC '92 Proceedings of the conference on European design automation
Boolean matching in logic synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
Routability-driven fanout optimization
DAC '93 Proceedings of the 30th international Design Automation Conference
The reproducing placement problem with applications
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A methodology and algorithms for post-placement delay optimization
DAC '94 Proceedings of the 31st annual Design Automation Conference
Technology mapping using fuzzy logic
DAC '94 Proceedings of the 31st annual Design Automation Conference
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Post-layout optimization for deep submicron design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Physical design CAD in deep sub-micron era
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Layout driven re-synthesis for low power consumption LSIs
DAC '97 Proceedings of the 34th annual Design Automation Conference
An exact solution to simultaneous technology mapping and linear placement problem
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Timing driven placement in interaction with netlist transformations
Proceedings of the 1997 international symposium on Physical design
Proceedings of the 1997 international symposium on Physical design
IEEE Transactions on Computers
M32: a constructive multilevel logic synthesis system
DAC '98 Proceedings of the 35th annual Design Automation Conference
Wireplanning in logic synthesis
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Integrating logic retiming and register placement
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Network flow based circuit partitioning for time-multiplexed FPGAs
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A timing-driven soft-macro resynthesis method in interaction with chip floorplanning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
An integrated algorithm for combined placement and libraryless technology mapping
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Synthesis for multiple input wires replacement of a gate for wiring consideration
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Technology mapping for minimizing gate and routing area
Proceedings of the conference on Design, automation and test in Europe
Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Understanding and addressing the impact of wiring congestion during technology mapping
Proceedings of the 2002 international symposium on Physical design
Logic Synthesis and Verification
Logical and physical design: a flow perspective
Logic Synthesis and Verification
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Addressing the timing closure problem by integrating logic optimization and placement
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Bounding the efforts on congestion optimization for physical synthesis
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
A study of netlist structure and placement efficiency
Proceedings of the 2004 international symposium on Physical design
Timing driven gate duplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Pre-layout wire length and congestion estimation
Proceedings of the 41st annual Design Automation Conference
An efficient technology mapping algorithm targeting routing congestion under delay constraints
Proceedings of the 2005 international symposium on Physical design
Wire length prediction-based technology mapping and fanout optimization
Proceedings of the 2005 international symposium on Physical design
A new incremental placement algorithm and its application to congestion-aware divisor extraction
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Delay-optimal simultaneous technology mapping and placement with applications to timing optimization
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
On the decreasing significance of large standard cells in technology mapping
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
On improving optimization effectiveness in interconnect-driven physical synthesis
Proceedings of the 2009 international symposium on Physical design
ECO timing optimization using spare cells and technology remapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
X-architecture obstacles-avoiding routing with ECO consideration
ICC'10 Proceedings of the 14th WSEAS international conference on Circuits
ECO-aware obstacle-avoiding routing tree algorithm
WSEAS Transactions on Circuits and Systems
Technology mapping with crosstalk noise avoidance
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
TRECO: dynamic technology remapping for timing engineering change orders
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Accurate area and delay estimation from RTL descriptions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |