Layout driven technology mapping
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Performance-oriented technology mapping
Performance-oriented technology mapping
An exact solution to simultaneous technology mapping and linear placement problem
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Timing driven placement in interaction with netlist transformations
Proceedings of the 1997 international symposium on Physical design
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Wireplanning in logic synthesis
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A novel VLSI layout fabric for deep sub-micron applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Concurrent logic restructuring and placement for timing closure
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
A Robust Solution to the Timing Convergence Problem in High-Performance Design
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Timing optimization of FPGA placements by logic replication
Proceedings of the 40th annual Design Automation Conference
Hybrid hierarchical timing closure methodology for a high performance and low power DSP
Proceedings of the 40th annual Design Automation Conference
Timing closure through a globally synchronous, timing partitioned design methodology
Proceedings of the 41st annual Design Automation Conference
An approach to placement-coupled logic replication
Proceedings of the 41st annual Design Automation Conference
A new incremental placement algorithm and its application to congestion-aware divisor extraction
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Techniques for improved placement-coupled logic replication
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Intrinsic shortest path length: a new, accurate a priori wirelength estimator
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Optimizing non-monotonic interconnect using functional simulation and logic restructuring
Proceedings of the 2008 international symposium on Physical design
Delay-optimal simultaneous technology mapping and placement with applications to timing optimization
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Fast, accurate a priori routing delay estimation
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Efficient post-layout power-delay curve generation
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation, logic synthesis and layout synthesis are iterated until the estimates match. The number of such iterations is becoming larger as technology scales. Timing closure problems occur mainly due to the difficulty in accurately predicting interconnect delay during logic synthesis.In this paper, we present an algorithm that integrates logic synthesis and global placement to address the timing closure problem. We introduce technology independent algorithms as well as technology dependent algorithms. Our technology independent algorithms are based on the notion of "wire-planning". All these algorithms interleave their logic operations with local and incremental/full global placement, in order to maintain a consistent placement while the algorithm is run. We show that by integrating logic synthesis and placement, we avoid the need to predict interconnect delay during logic synthesis. We demonstrate that our scheme significantly enhances the predictability of wire delays, thereby solving the timing closure problem. This is the main result of our paper. Our results also show that our algorithms result in a significant reduction in total circuit delay. In addition, our technology independent algorithms result in a significant circuit area reduction.