Optimizing non-monotonic interconnect using functional simulation and logic restructuring

  • Authors:

  • Stephen M. Plaza;Igor L. Markov;Valeria Bertacco

  • Affiliations:

  • University of Michigan, Ann Arbor, USA;University of Michigan, Ann Arbor, USA and National Taiwan University, Taipei, Taiwan;University of Michigan, Ann Arbor, USA

  • Venue:
  • Proceedings of the 2008 international symposium on Physical design
  • Year:
  • 2008

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Abstract

The relatively poor scaling of interconnect in modern digital circuits necessitates a number of design optimizations, which must typically be iterated several times to meet the specified performance objectives. Such iterations are often due to the difficulty of early delay estimation, especially before placement. Therefore, effective logic restructuring to reduce interconnect delay has been a major challenge in physical synthesis, a phase during which more accurate delay estimates can be finally gathered. In this work, we develop a new approach to this problem that enhances modern high performance logic synthesis techniques with flexibility and accuracy in the physical domain. This approach is based on (1) a novel criterion based on path monotonicity, that identifies those interconnects amenable to optimization through logic restructuring and (2) a synthesis algorithm relying on logic simulation and placement information to identify placed subcircuits that hold promise for interconnect reduction. Experiments indicate that our techniques find optimization opportunities and improve interconnect delay by 11.7% on average at less than 2% wirelength and area overhead