A methodology and algorithms for post-placement delay optimization

Optimal wire sizing and buffer insertion for low power and a generalized delay model

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Post-layout optimization for deep submicron design

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Buffered Steiner tree construction with wire sizing for interconnect layout optimization

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Physical design CAD in deep sub-micron era

EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation

Useful-Skew Clock Routing with Gate Sizing for Low Power Design

Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks

Wire segmenting for improved buffer insertion

DAC '97 Proceedings of the 34th annual Design Automation Conference

Layout driven re-synthesis for low power consumption LSIs

DAC '97 Proceedings of the 34th annual Design Automation Conference

Delay bounded buffered tree construction for timing driven floorplanning

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Timing driven placement in interaction with netlist transformations

Proceedings of the 1997 international symposium on Physical design

A practical repeater insertion method in high speed VLSI circuits

DAC '98 Proceedings of the 35th annual Design Automation Conference

Simultaneous routing and buffer insertion with restrictions on buffer locations

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Using partitioning to help convergence in the standard-cell design automation methodology

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

A methodology for correct-by-construction latency insensitive design

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

Transformational placement and synthesis

DATE '00 Proceedings of the conference on Design, automation and test in Europe

Understanding and addressing the impact of wiring congestion during technology mapping

Proceedings of the 2002 international symposium on Physical design

Technology-based transformations

Logic Synthesis and Verification

On mismatches between incremental optimizers and instance perturbations in physical design tools

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

Layout-driven area-constrained timing optimization by net buffering

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

Bounding the efforts on congestion optimization for physical synthesis

Proceedings of the 13th ACM Great Lakes symposium on VLSI

Layout-driven Timing Optimization by Generalized De Morgan Transform

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference

Techniques that Improved the Timing Convergence of the Gekko PowerPC Microprocessor

ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design

An area-efficient timing closure technique for FPGAs using Shannon's expansion

Integration, the VLSI Journal

Optimizing non-monotonic interconnect using functional simulation and logic restructuring

Proceedings of the 2008 international symposium on Physical design

SafeResynth: A new technique for physical synthesis

Integration, the VLSI Journal

Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design