A technology mapping method based on perfect and semi-perfect matchings
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Layout driven technology mapping
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A methodology and algorithms for post-placement delay optimization
DAC '94 Proceedings of the 31st annual Design Automation Conference
Technology mapping using fuzzy logic
DAC '94 Proceedings of the 31st annual Design Automation Conference
Multilevel logic optimization of very high complexity circuits
EURO-DAC '94 Proceedings of the conference on European design automation
M32: a constructive multilevel logic synthesis system
DAC '98 Proceedings of the 35th annual Design Automation Conference
Logic Synthesis and Verification
Metrics for structural logic synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
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This paper presents a multilevel synthesis method on standard cells aiming at reducing both gate and wiring areas. The goal is to decrease the routing factor which is defined as the ratio between the routing area and the gate area. The wiring is taken into account during the synthesis steps (factorization and technology mapping). The approach is based on lexicographical expression of Boolean function controlling input dependency, and on kernel filtering controlling excessive factorizations responsible for wiring complexity increase.