Multilevel synthesis minimizing the routing factor
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Wireplanning in logic synthesis
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Proceedings of the tenth annual ACM-SIAM symposium on Discrete algorithms
Congestion aware layout driven logic synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Faster minimization of linear wirelength for global placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Understanding metrics in logic synthesis for routability enhancement
Proceedings of the 2003 international workshop on System-level interconnect prediction
Benchmarking for large-scale placement and beyond
Proceedings of the 2003 international symposium on Physical design
Design topology aware physical metrics for placement analysis
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Physical synthesis methodology for high performance microprocessors
Proceedings of the 40th annual Design Automation Conference
A study of netlist structure and placement efficiency
Proceedings of the 2004 international symposium on Physical design
A predictive distributed congestion metric and its application to technology mapping
Proceedings of the 2004 international symposium on Physical design
Implicit enumeration of structural changes in circuit optimization
Proceedings of the 41st annual Design Automation Conference
Pre-layout wire length and congestion estimation
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2005 international symposium on Physical design
An efficient technology mapping algorithm targeting routing congestion under delay constraints
Proceedings of the 2005 international symposium on Physical design
Wire length prediction-based technology mapping and fanout optimization
Proceedings of the 2005 international symposium on Physical design
uComplexity: Estimating Processor Design Effort
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
A new incremental placement algorithm and its application to congestion-aware divisor extraction
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Intrinsic shortest path length: a new, accurate a priori wirelength estimator
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Fast, accurate a priori routing delay estimation
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Detecting tangled logic structures in VLSI netlists
Proceedings of the 47th Design Automation Conference
Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Routability or wiring congestion in a VLSI chip is becoming increasingly important as chip complexity increases. Congestion has a significant impact on performance, yield and chip area. Although advances in placement algorithms have attempted to alleviate this problem, the inherent structure of the logic netlist has a significant impact on the routability irrespective of the placement algorithm used. Placement algorithms find optimal assignment of locations to the logic and do not have the ability to change the netlist structure. Significant decisions regarding the circuit structure are made early in synthesis such as during the technology independent logic optimization step. Optimizations in this step use literal count as a metric for optimization and do not adequately capture the intrinsic entanglement of the netlist. Two circuits with identical literal counts may have significantly different congestion characteristics post placement. In this paper, we motivate that a property of the network structure called adhesion can make a significant contribution to routing congestion. We then provide a metric to measure this property. We also show that adhesion as measured by this metric can be used in addition to literal counts to estimate and optimize post routing congestion early in the design flow.