A wire length estimation technique utilizing neighborhood density equations
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Pre-layout estimation of individual wire lengths
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Edge separability based circuit clustering with application to circuit partitioning
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Toward better wireload models in the presence of obstacles
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Addressing the timing closure problem by integrating logic optimization and placement
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Accurate pseudo-constructive wirelength and congestion estimation
Proceedings of the 2003 international workshop on System-level interconnect prediction
Metrics for structural logic synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Wire length prediction based clustering and its application in placement
Proceedings of the 40th annual Design Automation Conference
Probabilistic congestion prediction
Proceedings of the 2004 international symposium on Physical design
Toward the accurate prediction of placement wire length distributions in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fitted Elmore delay: a simple and accurate interconnect delay model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Intrinsic shortest path length: a new, accurate a priori wirelength estimator
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
| Hi-index | 0.00 |
We propose in this paper a novel approach for speeding timing closure. We focus on the problem of accurate post-routing delay estimation from a given placement. Post-routing delays differ from placement delays due to factors such as net topology, layer assignment and congestion. Fundamental to our approach is utilizing an existing base design to predict future designs. We present four wire-delay estimation techniques based on: delay fitting, Steiner-aware delay fitting, Steiner-aware RC sampling, and scaled Steiner-aware RC sampling. We apply our techniques to several designs, and using an industrial flow, we demonstrate that it is possible to estimate the routing delays with an average estimation error of 16% on benchmark circuits. These results are of practical value, and improve on the state-of-the-art industrial estimation capabilities.