A priori system-level interconnect prediction: Rent's rule and wire length distribution models
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SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
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Proceedings of the 2003 international workshop on System-level interconnect prediction
Proceedings of the 2003 international workshop on System-level interconnect prediction
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Proceedings of the 19th ACM Great Lakes symposium on VLSI
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Fast, accurate a priori routing delay estimation
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Journal of Systems Architecture: the EUROMICRO Journal
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A system-on-a-chip (SoC) contains several pre-designed heterogeneous megacells that have been designed and routed optimally. In this paper a new stochastic net-length distribution for global interconnects in a nonhomogeneous SoC is derived using novel models for netlist, placement, and routing information. The netlist information is rigorously derived based on heterogeneous Rent's rule, the placement information is modeled by assuming a random placement of terminals for a given net in a bounding area, and the routing information is constructed based on a new model for minimum rectilinear Steiner tree construction (MRST). The combination of the three models gives a priori estimation of global net-length distribution in a heterogeneous SoC. Unlike previous models that empirically relate the average length of the global wires to the chip area, the new distribution provides a complete and accurate distribution of net-length for global interconnects. Through comparison with actual product data, it is shown that the new stochastic model successfully predicts the global net-length distribution of a heterogeneous system.