Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
VISI Physical Design Automation: Theory and Practice
VISI Physical Design Automation: Theory and Practice
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In this work two way partitioning of a circuit represented as a graph, is made using simulated annealing procedure and delay between the partitions is minimized. The various parameters used in the annealing process like initial temperature, cooling rate, and the threshold, given as a number of calculations, are changed and its influence on the delay between the partitions is discussed. Procedure was tested on an example with a 102 components connected by 103 nets. Substantial improvement in delay is obtained over the initial circuit delay proving the effectiveness of proposed method.