Timing influenced force directed floorplanning
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
On convex formulation of the floorplan area minimization problem
ISPD '98 Proceedings of the 1998 international symposium on Physical design
A methodology for fast FPGA floorplanning
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
A performance-driven standard-cell placer based on a modified force-directed algorithm
Proceedings of the 2001 international symposium on Physical design
A minimum cost path search algorithm through tile obstacles
Proceedings of the 2001 international symposium on Physical design
TCG: a transitive closure graph-based representation for non-slicing floorplans
Proceedings of the 38th annual Design Automation Conference
An effective congestion driven placement framework
Proceedings of the 2002 international symposium on Physical design
A branch-and-price algorithm for the Steiner tree packing problem
Computers and Operations Research
Parallelizing Tabu Search on a Cluster of Heterogeneous Workstations
Journal of Heuristics
On Using Tabu Search for Design Automation of VLSI Systems
Journal of Heuristics
Fuzzy simulated evolution algorithm for VLSI cell placement
Computers and Industrial Engineering - Special issue: Focussed issue on applied meta-heuristics
A Genetic Algorithm for Switchbox Routing Problem
RSCTC '98 Proceedings of the First International Conference on Rough Sets and Current Trends in Computing
A Datapath Generator for Full-Custom Macros of Iterative Logic Arrays
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Macro Block Based FPGA Floorplanning
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Reducing Library Development Cycle Time through an Optimum Layout Create Flow
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Constructive Floorplanning with a Yield Objective
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Modern floorplanning based on fast simulated annealing
Proceedings of the 2005 international symposium on Physical design
Aladin: A Layout Synthesys Tool for Analog Integrated Circuits
Analog Integrated Circuits and Signal Processing
Silicon virtual prototyping: the new cockpit for nanometer chip design
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A low complexity heuristic for design of custom network-on-chip architectures
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Droplet routing in the synthesis of digital microfluidic biochips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Module placement for fault-tolerant microfluidics-based biochips
Proceedings of the 41st annual Design Automation Conference
Linear-programming-based techniques for synthesis of network-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient quadratic placement based on search space traversing technology
Integration, the VLSI Journal
A fast algorithm for rectilinear block packing based on selected sequence-pair
Integration, the VLSI Journal
Integrated Computer-Aided Engineering
Module assignment for pin-limited designs under the stacked-Vdd paradigm
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2008 international symposium on Physical design
Integrated droplet routing and defect tolerance in the synthesis of digital microfluidic biochips
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Graph partitioning through a multi-objective evolutionary algorithm: a preliminary study
Proceedings of the 10th annual conference on Genetic and evolutionary computation
Automated module assignment in stacked-Vdd designs for high-efficiency power delivery
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Octagonal drawings of plane graphs with prescribed face areas
Computational Geometry: Theory and Applications
Generating All Triangulations of Plane Graphs (Extended Abstract)
WALCOM '09 Proceedings of the 3rd International Workshop on Algorithms and Computation
Drawing slicing graphs with face areas
Theoretical Computer Science
Evolutionary algorithms for VLSI multi-objective netlist partitioning
Engineering Applications of Artificial Intelligence
A metal-only-ECO solver for input-slew and output-loading violations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Register file partitioning and recompilation for register file power reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simulated annealing based VLSI circuit partitioning for delay minimization
CI'10 Proceedings of the 4th WSEAS international conference on Computational intelligence
Placement and Floorplanning in Dynamically Reconfigurable FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Cross-contamination avoidance for droplet routing in digital microfluidic biochips
Proceedings of the Conference on Design, Automation and Test in Europe
Algorithms and theory of computation handbook
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Register file partitioning and compiler support for reducing embedded processor power consumption
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cut-demand based routing resource allocation and consolidation for routability enhancement
Proceedings of the 16th Asia and South Pacific Design Automation Conference
TCG: a transitive closure graph-based representation for general floorplans
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An automated design tool for analog layouts
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Floorplanning considering IR drop in multiple supply voltages island designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An auction based pre-processing technique to determine detour in global routing
Proceedings of the International Conference on Computer-Aided Design
Inner rectangular drawings of plane graphs
ISAAC'04 Proceedings of the 15th international conference on Algorithms and Computation
Octagonal drawings of plane graphs with prescribed face areas
WG'04 Proceedings of the 30th international conference on Graph-Theoretic Concepts in Computer Science
ICAISC'06 Proceedings of the 8th international conference on Artificial Intelligence and Soft Computing
A parallel tabu search algorithm for optimizing multiobjective VLSI placement
ICCSA'05 Proceedings of the 2005 international conference on Computational Science and Its Applications - Volume Part IV
Netlist bipartitioning using particle swarm optimisation technique
International Journal of Artificial Intelligence and Soft Computing
Architectural synthesis of flow-based microfluidic large-scale integration biochips
Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems
Dynamic partitioning of IP-based wireless access networks
Computer Networks: The International Journal of Computer and Telecommunications Networking
Cell assignment in hybrid CMOS/nanodevices architecture using Tabu Search
Applied Intelligence
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From the Publisher:VLSI is an important area of electronic and computer engineering: however, there are few textbooks available for undergraduate education in VLSI design automation and chip layout. VLSI Physical Design Automation fills the void and is an essential introduction for senior undergraduates, postgraduates and anyone starting work in the field of CAD for VLSI. It covers all aspects of physical design, together with such related areas as automatic cell generation, silicon compilation, layout editors and compaction. A problem solving approach has been adopted and each solution has been illustrated with examples. Each topic is treated in a standard format of Problem Definition, Cost Functions and Constraints, Possible Approaches and Latest Developments.