An optimal algorithm for floorplan area optimization
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Branch-and-bound placement for building block layout
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Module placement on BSG-structure and IC layout applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An enhanced perturbing algorithm for floorplan design using the O-tree representation
ISPD '00 Proceedings of the 2000 international symposium on Physical design
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
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Proceedings of the 2001 Asia and South Pacific Design Automation Conference
VISI Physical Design Automation: Theory and Practice
VISI Physical Design Automation: Theory and Practice
Corner block list: an effective and efficient topological representation of non-slicing floorplan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
DAC '82 Proceedings of the 19th Design Automation Conference
Area minimization for floorplans
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Consistent placement of macro-blocks using floorplanning and standard-cell placement
Proceedings of the 2002 international symposium on Physical design
TCG-S: orthogonal coupling of P*-admissible representations for general floorplans
Proceedings of the 39th annual Design Automation Conference
Microarchitecture evaluation with physical planning
Proceedings of the 40th annual Design Automation Conference
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Proceedings of the 40th annual Design Automation Conference
Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An area-optimality study of floorplanning
Proceedings of the 2004 international symposium on Physical design
Recursive bisection based mixed block placement
Proceedings of the 2004 international symposium on Physical design
Stairway compaction using corner block list and its applications with rectilinear blocks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Space-planning: placement of modules with controlled empty area by single-sequence
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
On handling arbitrary rectilinear shape constraint
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Temporal floorplanning using 3D-subTCG
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Combinatorial techniques for mixed-size placement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Are floorplan representations important in digital design?
Proceedings of the 2005 international symposium on Physical design
Fast evaluation of bounded slice-line grid
Journal of Computer Science and Technology
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Simultaneous block and I/O buffer floorplanning for flip-chip design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An automated design flow for 3D microarchitecture evaluation
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A fixed-die floorplanning algorithm using an analytical approach
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Multi-level placement for large-scale mixed-size IC designs
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Fast floorplanning by look-ahead enabled recursive bipartitioning
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
LFF algorithm for heterogeneous FPGA floorplanning
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal redistribution of white space for wire length minimization
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Interconnect estimation without packing via ACG floorplans
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Block alignment in 3D floorplan using layered TCG
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Module placement for fault-tolerant microfluidics-based biochips
Proceedings of the 41st annual Design Automation Conference
A revisit to floorplan optimization by Lagrangian relaxation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A new heuristic algorithm for rectangle packing
Computers and Operations Research
Temporal floorplanning using the three-dimensional transitive closure subGraph
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Multi-bend bus driven floorplanning
Integration, the VLSI Journal
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
TCG-based multi-bend bus driven floorplanning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Effective decap insertion in area-array SoC floorplan design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Block flipping and white space distribution for wirelength minimization
Integration, the VLSI Journal
Linear constraint graph for floorplan optimization with soft blocks
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A novel fixed-outline floorplanner with zero deadspace for hierarchical design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Constraint graph-based macro placement for modern mixed-size circuit designs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Toolset for nano-reconfigurable computing
Microelectronics Journal
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Discrete PSO for Multi-objective Optimization in VLSI Floorplanning
ISICA '09 Proceedings of the 4th International Symposium on Advances in Computation and Intelligence
Bus via reduction based on floorplan revising
Proceedings of the 20th symposium on Great lakes symposium on VLSI
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Integration, the VLSI Journal
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Proceedings of the Conference on Design, Automation and Test in Europe
UFO: unified convex optimization algorithms for fixed-outline floorplanning
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
TCG: a transitive closure graph-based representation for general floorplans
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A quick generation method of sequence pair for block placement
ICCS'05 Proceedings of the 5th international conference on Computational Science - Volume Part III
An improved algorithm for sequence pair generation
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part I
MDE-based FPGA physical design: fast model-driven prototyping with Smalltalk
Proceedings of the International Workshop on Smalltalk Technologies
On improved least flexibility first heuristics superior for packing and stock cutting problems
SAGA'05 Proceedings of the Third international conference on StochasticAlgorithms: foundations and applications
Accurate process-hotspot detection using critical design rule extraction
Proceedings of the 49th Annual Design Automation Conference
LAYGEN II: automatic analog ICs layout generator based on a template approach
Proceedings of the 14th annual conference on Genetic and evolutionary computation
Hierarchical congregated ant system for bottom-up VLSI placements
Engineering Applications of Artificial Intelligence
Multi-bend bus-driven floorplanning considering fixed-outline constraints
Integration, the VLSI Journal
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In this paper, we propose a transitive closure graph-based representation for general floorplans, called TCG, and show its superior properties. TCG combines the advantages of popular representations such as sequence pair, BSG, and B*-tree. Like sequence pair and BSG, but unlike O-tree, B*-tree, and CBL, TCG is P-admissible. Like B*-tree, but unlike sequence pair, BSG, O-tree, and CBL, TCG does not need to construct additional constraint graphs for the cost evaluation during packing, implying faster runtime. Further, TCG supports incremental update during operations and keeps the information of boundary modules as well as the shapes and the relative positions of modules in the representation. More importantly, the geometric relation among modules is transparent not only to the TCG representation but also to its operations, facilitating the convergence to a desired solution. All these properties make TCG an effective and flexible representation for handling the general floorplan/placement design problems with various constraints. Experimental results show the promise of TCG.