Solutions to the module orientation and rotation problems by neural computation networks
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
The Orientation of Modules Based on Graph Decomposition
IEEE Transactions on Computers
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Fast evaluation of sequence pair in block placement by longest common subsequence computation
DATE '00 Proceedings of the conference on Design, automation and test in Europe
TCG: a transitive closure graph-based representation for non-slicing floorplans
Proceedings of the 38th annual Design Automation Conference
Flipping Modules to Minimize Maximum Wire Length
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Optimal redistribution of white space for wire length minimization
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Wirelength optimization by optimal block orientation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Optimal cell flipping in placement and floorplanning
Proceedings of the 43rd annual Design Automation Conference
Area reduction by deadspace utilization on interconnect optimized floorplan
ACM Transactions on Design Automation of Electronic Systems (TODAES)
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Floorplanning plays an important role in the physical design of very large scale integration (VLSI) circuits. Traditional floorplanners use heuristics to optimize a floorplan based on multiple objectives. Besides traditional floorplanning approaches, some post-floorplanning steps can be applied to consider block flipping, pin assignment and white space distribution to optimize the performance. If we can consider the above three optimizations simultaneously as a post-floorplanning step, the total wirelength can be further reduced without modifying the original floorplan topology. Experimental results show that our approach can handle these issues simultaneously and wirelength can be further improved with a small penalty in runtime. Thus, this approach is highly desirable to be incorporated into a floorplanner as a post-processing step for wirelength optimization.