Solutions to the module orientation and rotation problems by neural computation networks
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
VLSI cell placement techniques
ACM Computing Surveys (CSUR)
The Orientation of Modules Based on Graph Decomposition
IEEE Transactions on Computers
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Automatic placement a review of current techniques (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Algorithms and Data Structures in VLSI Design
Algorithms and Data Structures in VLSI Design
LTX - a system for the directed automatic design of LSI circuits
DAC '76 Proceedings of the 13th Design Automation Conference
A simple yet effective genetic approach for the orientation assignment on cell-based layout
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Solution of a module orientation and rotation problem
EURO-DAC '90 Proceedings of the conference on European design automation
Interconnect-driven floorplanning by searching alternative packings
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An evolutionary neural network approach for module orientationproblems
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal cell flipping in placement and floorplanning
Proceedings of the 43rd annual Design Automation Conference
Block flipping and white space distribution for wirelength minimization
Integration, the VLSI Journal
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Rectangular cells can be flipped in place along either horizontal or vertical axis without changing the area of a layout. During floorplanning, both the location and orientation of cells are determined. However, the complexity of the floorplanning process usually means that the wirelength is not minimum. This paper proposes a technique for wirelength minimization based on in-place flipping of cells that can be applied to any floorplan style consisting of rectangular blocks or sub-blocks. Instead of conventional search procedures, a Boolean symbolic approach is proposed to generate flip-optimal floorplans. Experimental results show that it can effectively reduce the wirelength of current state of the art approaches, at no cost in area and with modest runtimes.