GRAFOS - A symbolic routing language
DAC '73 Proceedings of the 10th Design Automation Workshop
PRO - an automatic string placement program for polycell layout
DAC '76 Proceedings of the 13th Design Automation Conference
DAC '76 Proceedings of the 13th Design Automation Conference
Clustering and linear placement
DAC '72 Proceedings of the 9th Design Automation Workshop
A high quality, low cost router for MOS/LSI
DAC '72 Proceedings of the 9th Design Automation Workshop
Operational features of an MOS timing simulator
DAC '75 Proceedings of the 12th Design Automation Conference
A 2-dimensional placement algorithm for the layout of electrical circuits
25 years of DAC Papers on Twenty-five years of electronic design automation
25 years of DAC Papers on Twenty-five years of electronic design automation
FLOSS: an approach to automated layout for high-volume designs
25 years of DAC Papers on Twenty-five years of electronic design automation
VLSI cell placement techniques
ACM Computing Surveys (CSUR)
Improved channel routing by via minimization and shifting
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Near-optimal n-layer channel routing
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Reducing channel density in standard cell layout
DAC '83 Proceedings of the 20th Design Automation Conference
Design aids for the simulation of bipolar gate arrays
DAC '83 Proceedings of the 20th Design Automation Conference
Linear ordering and application to placement
DAC '83 Proceedings of the 20th Design Automation Conference
A wire routing scheme for double-layer cell arrays
DAC '84 Proceedings of the 21st Design Automation Conference
A high level synthesis tool for MOS chip design
DAC '84 Proceedings of the 21st Design Automation Conference
DAC '84 Proceedings of the 21st Design Automation Conference
The Hughes Automated Layout System - automated LSI/VLSI layout based on channel routing
DAC '81 Proceedings of the 18th Design Automation Conference
Methods for hierarchical automatic layout of custom LSI circuit masks
DAC '78 Proceedings of the 15th Design Automation Conference
DAC '80 Proceedings of the 17th Design Automation Conference
DAC '80 Proceedings of the 17th Design Automation Conference
DAC '80 Proceedings of the 17th Design Automation Conference
A 2-dimensional placement algorithm for the layout of electrical circuits.
DAC '76 Proceedings of the 13th Design Automation Conference
PRO - an automatic string placement program for polycell layout
DAC '76 Proceedings of the 13th Design Automation Conference
DAC '76 Proceedings of the 13th Design Automation Conference
Floss: An approach to automated layout for high-volume designs
DAC '77 Proceedings of the 14th Design Automation Conference
A class of min-cut placement algorithms
DAC '77 Proceedings of the 14th Design Automation Conference
A new two-dimensional routing algorithm
DAC '82 Proceedings of the 19th Design Automation Conference
DORA:: CAD interface to automatic diagnostics
DAC '82 Proceedings of the 19th Design Automation Conference
Automated layout in ASHLAR: An approach to the problems of “General Cell” layout for VLSI
DAC '82 Proceedings of the 19th Design Automation Conference
Hierarchical top-down layout design method for VLSI chip
DAC '82 Proceedings of the 19th Design Automation Conference
CGALA-a multi technology Gate Array Layout system
DAC '82 Proceedings of the 19th Design Automation Conference
CALMOS: A portable software system for the automatic and interactive layout of MOS/LSI
DAC '79 Proceedings of the 16th Design Automation Conference
Optimal layout of CMOS functional arrays
DAC '79 Proceedings of the 16th Design Automation Conference
MIRAGE - a simple-model routing program for the hierarchical layout design of IC masks
DAC '79 Proceedings of the 16th Design Automation Conference
Wirelength optimization by optimal block orientation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Optimal Layout of CMOS Functional Arrays
IEEE Transactions on Computers
A computer-aided VLSI layout system
AFIPS '81 Proceedings of the May 4-7, 1981, national computer conference
Number of vias: a control parameter for global wiring of high-density chips
IBM Journal of Research and Development
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LTX is a minicomputer-based design system for large-scale integrated circuit chip layout which offers a flexible set of interactive and automatic procedures for translating a circuit connectivity description into a finished mask design. The system encompasses algorithms for two-dimensional placement, string placement, exploitation of equivalent terminals, decomposition of routing into channels, and channel routing. Circuit connectivity is preserved during interactive procedures. LTX runs on an H-P 2100 series computer with 32K of memory and disc. In current applications to polycell-style layouts, one to two weeks is typically required for completion of the layout design of an LSI chip containing 500 cells.