A line-expansion algorithm for the general routing problem with a guaranteed solution
DAC '80 Proceedings of the 17th Design Automation Conference
LTX - a system for the directed automatic design of LSI circuits
DAC '76 Proceedings of the 13th Design Automation Conference
DAC '76 Proceedings of the 13th Design Automation Conference
A solution to line-routing problems on the continuous plane
DAC '69 Proceedings of the 6th annual Design Automation Conference
DAC '79 Proceedings of the 16th Design Automation Conference
A channel/switchbox definition algorithm for building-block layout
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A multi-layer router utilizing over-cell areas
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
On minimizing the number of L-shaped channels
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An Efficient VLSI Switch-Box Router
IEEE Design & Test
A wire routing scheme for double-layer cell arrays
DAC '84 Proceedings of the 21st Design Automation Conference
A symbolic-interconnect router for custom IC design
DAC '84 Proceedings of the 21st Design Automation Conference
Two-dimensional channel routing and channel intersection problems
DAC '82 Proceedings of the 19th Design Automation Conference
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A new heuristic algorithm for two-dimensional routing utilizing two distinct layers is described. It is assumed that all terminals are on the boundary of a rectilinear routing region with or without cutout sections. Terminals on vertical boundary segments are assumed to be on one layer and those on horizontal boundary segments are on the other layer. This algorithm finds all possible paths with minimum corners for a net and then chooses one of those paths by considering path length, the likelihood of blocking nets not yet routed, the usage of vacant tracks, and the necessity of going through an area expected to be congested. A dynamic data structure is maintained. If h and v are the numbers of horizontal and vertical tracks, n is the number of nets, and t is the number of terminals, then the storage requirement is o(hv) and the time complexity is o((t−n)hv). For h&equil;23, v&equil;64, n&equil;47, and t&equil;130 the storage required is 60K bytes and cpu time is 16 seconds. This algorithm is implemented in the C language on a VAX 11/780 under the Berkeley Unix* operating system, as part of the LTX layout system of the layout aids group at Bell Laboratories, Murray Hill.