Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
SHARPS: A hierarchical layout system for VLSI
DAC '81 Proceedings of the 18th Design Automation Conference
A new two-dimensional routing algorithm
DAC '82 Proceedings of the 19th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
On minimizing the number of L-shaped channels
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Slicible rectangular graphs and their optimal floorplans
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Monotone bipartitioning problem in a planar point set with applications to VLSI
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Geometric bipartitioning problem and its applications to VLSI
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
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In this paper we study the problem of routing region definition in the VLSI building-block layout design style. We present an algorithm to decompose the routing area into a set of straight channels and switchboxes such that the number of switchboxes in the decomposition is minimized. Our algorithm is based on a graph-theoretic approach that makes use of an efficient polynomial time optimal algorithm for computing minimum clique covers of triangulated graphs. Experimental results indicate our algorithm performs well. We compared our algorithm with a previously known greedy approach and an exhaustive search optimal algorithm. For all the test problems we considered, our algorithm consistently outperformed the greedy algorithm, and it produced optimal solutions in almost all cases.