Multidimensional binary search trees used for associative searching
Communications of the ACM
An application of exploratory data analysis techniques to floorplan design
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Minimum-Area Wiring for Slicing Structures
IEEE Transactions on Computers
VLSI leaf cell design by understanding circuit structures
IEA/AIE '89 Proceedings of the 2nd international conference on Industrial and engineering applications of artificial intelligence and expert systems - Volume 1
Efficient floorplan area optimization
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A graph theoretic technique to speed up floorplan area optimization
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
An optimal algorithm for floorplan area optimization
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
An analytical approach to floorplan design and optimization
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A channel/switchbox definition algorithm for building-block layout
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
On minimizing the number of L-shaped channels
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Branch-and-bound placement for building block layout
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Flexible controlpath microarchitecture synthesis based on artificial intelligence
EURO-DAC '92 Proceedings of the conference on European design automation
Area minimization for hierarchical floorplans
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An optimal algorithm for area minimization of slicing floorplans
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Efficient approximation algorithms for floorplan area minimization
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Hybrid floorplanning based on partial clustering and module restructuring
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Module placement on BSG-structure and IC layout applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Performance driven floorplanning for FPGA based designs
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
DAC '97 Proceedings of the 34th annual Design Automation Conference
How good are slicing floorplans?
Proceedings of the 1997 international symposium on Physical design
Device-level early floorplanning algorithms for RF circuits
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Automatic building of graphs for rectangular dualisation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Slicing floorplans with pre-placed modules
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Arbitrary rectilinear block packing based on sequence pair
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Slicing floorplans with range constraint
ISPD '99 Proceedings of the 1999 international symposium on Physical design
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Hierarchial global wiring for custom chip design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Flute—a floorplanning agent for full custom VLSI design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Automatic placement a review of current techniques (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Classical floorplanning harmful?
ISPD '00 Proceedings of the 2000 international symposium on Physical design
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Integrated floorplanning and interconnect planning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Copyright protection of designs based on multi source IPs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Slicing tree is a complete floorplan representation
Proceedings of the conference on Design, automation and test in Europe
Faster and more accurate wiring evaluation in interconnect-centric floorplanning
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Slicing floorplan design with boundary-constrained modules
Proceedings of the 2001 international symposium on Physical design
Revisiting floorplan representations
Proceedings of the 2001 international symposium on Physical design
Slicing floorplan with clustering constraints
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Integrated power supply planning and floorplanning
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Some issues raised in physical design workshop 1987
ACM SIGDA Newsletter
TCG: a transitive closure graph-based representation for non-slicing floorplans
Proceedings of the 38th annual Design Automation Conference
Efficient list-approximation techniques for floorplan area minimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
TCG-S: orthogonal coupling of P*-admissible representations for general floorplans
Proceedings of the 39th annual Design Automation Conference
Floorplanning with alignment and performance constraints
Proceedings of the 39th annual Design Automation Conference
Floorplan representations: Complexity and connections
ACM Transactions on Design Automation of Electronic Systems (TODAES)
PIAF: Efficient IC Floor Planning
IEEE Expert: Intelligent Systems and Their Applications
Constrained "Modern" Floorplanning
Proceedings of the 2003 international symposium on Physical design
The optimisation of block layout and aisle structure by a genetic algorithm
Computers and Industrial Engineering
Rectilinear block placement using B*-trees
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multilevel floorplanning/placement for large-scale modules using B*-trees
Proceedings of the 40th annual Design Automation Conference
Placement of circuit modules using a graph space approach
DAC '83 Proceedings of the 20th Design Automation Conference
Computer-aided partitioning of behavioral hardware descriptions
DAC '83 Proceedings of the 20th Design Automation Conference
Macro Block Based FPGA Floorplanning
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
An Upper Bound for 3D Slicing Floorplans
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Rectilinear Block Placement Using B*-Trees
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Optimal slicing of plane point placements
EURO-DAC '90 Proceedings of the conference on European design automation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An area-optimality study of floorplanning
Proceedings of the 2004 international symposium on Physical design
Innovate or perish: FPGA physical design
Proceedings of the 2004 international symposium on Physical design
Multi-Million Gate FPGA Physical Design Challenges
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Space-planning: placement of modules with controlled empty area by single-sequence
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
On handling arbitrary rectilinear shape constraint
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Floorplan design for multi-million gate FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Fast floorplanning by look-ahead enabled recursive bipartitioning
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Floorplanning for 3-D VLSI design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal redistribution of white space for wire length minimization
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Post-placement voltage island generation under performance requirement
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A revisit to floorplan optimization by Lagrangian relaxation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
A novel fixed-outline floorplanner with zero deadspace for hierarchical design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Solving facility layout problems using genetic programming
GECCO '96 Proceedings of the 1st annual conference on Genetic and evolutionary computation
Analog layout generator for CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast unified floorplan topology generation and sizing on heterogeneous FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A tree based novel representation for 3D-block packing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient macro-cell placement algorithm
Integration, the VLSI Journal
How good are slicing floorplans?
Integration, the VLSI Journal
A SVD-based fragile watermarking scheme for image authentication
IWDW'02 Proceedings of the 1st international conference on Digital watermarking
Multi-objective floorplanning based on fuzzy logic
FSKD'09 Proceedings of the 6th international conference on Fuzzy systems and knowledge discovery - Volume 4
UFO: unified convex optimization algorithms for fixed-outline floorplanning
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
TCG: a transitive closure graph-based representation for general floorplans
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hotspots elimination and temperature flattening in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A theoretical upper bound for IP-based floorplanning
COCOON'05 Proceedings of the 11th annual international conference on Computing and Combinatorics
An improved algorithm for sequence pair generation
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part I
A genetic algorithm for VLSI floorplanning using o-tree representation
EC'05 Proceedings of the 3rd European conference on Applications of Evolutionary Computing
Scalable hierarchical floorplanning for fast physical prototyping of systems-on-chip
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Hierarchical congregated ant system for bottom-up VLSI placements
Engineering Applications of Artificial Intelligence
Constraint-aware interior layout exploration for pre-cast concrete-based buildings
The Visual Computer: International Journal of Computer Graphics
Routing analog ICs using a multi-objective multi-constraint evolutionary approach
Analog Integrated Circuits and Signal Processing
Template coding with LDS and applications of LDS in EDA
Analog Integrated Circuits and Signal Processing
A survey on B*-Tree-based evolutionary algorithms for VLSI floorplanning optimisation
International Journal of Computer Applications in Technology
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The problem of allocating area to modules at the highest level of a top-down decomposition is treated in this paper. A theorem of Schoenberg is applied to obtain a good embedding of the module space into the plane. The dutch metric is introduced to transform netlist information - if available - into a distance matrix. This metric is flexible enough to enable the user to steer the design in an interactive environment, and rigorous enough to yield results satisfying optimality criterions. The embedding is used to derive the topology of the floorplan in the form of the structure tree of a slicing structure. To store the partial structure tree during the construction a concise and convenient data structure, the shorthand tree, is introduced. For any aspect ratio of the chip a minimum area floorplan can be generated. The paper also shows how wiring space predictions can be incorporated, how varying degrees of module flexibility can be accounted for, and how fixing bonding pad macros affects the procedure.