Use of sensitivities and generalized substrate models in mixed-signal IC design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Module placement on BSG-structure and IC layout applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Generalized constraint generation for analog circuit design
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Module placement for analog layout using the sequence-pair representation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Layout-oriented synthesis of high performance analog circuits
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Slicing tree is a complete floorplan representation
Proceedings of the conference on Design, automation and test in Europe
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
Force directed mongrel with physical net constraints
Proceedings of the 40th annual Design Automation Conference
A solution to line-routing problems on the continuous plane
DAC '69 Proceedings of the 6th annual Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
Rectilinear Block Placement Using B*-Trees
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio
Proceedings of the conference on Design, automation and test in Europe
Automatic Device Layout Generation for Analog Layout Retargeting
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Formulating the Empirical Strategies in Module Generation of Analog MOS Layout
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Aladin: A Layout Synthesys Tool for Analog Integrated Circuits
Analog Integrated Circuits and Signal Processing
Signal-path driven partition and placement for analog circuit
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
New layout strategies with improved matching performance
Analog Integrated Circuits and Signal Processing
An automated design tool for analog layouts
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Net-based force-directed macrocell placement for wirelength optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Floorplanning using a tree representation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilevel symmetry-constraint generation for retargeting large analog layouts
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Placement Algorithm in Analog-Layout Designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Force-Directed Methods for Generic Placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LAYGEN II: automatic analog ICs layout generator based on a template approach
Proceedings of the 14th annual conference on Genetic and evolutionary computation
LASER: layout-aware analog synthesis environment on laker
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
ITRS 2011 analog EDA challenges and approaches
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Routing analog ICs using a multi-objective multi-constraint evolutionary approach
Analog Integrated Circuits and Signal Processing
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In this paper, we present a new layout level automation tool for analog CMOS circuits, namely, analog layout generator (ALG). ALG is capable of generating individual or matched components as well as placement and routing. ALG takes performance considerations into account, optimizing the layout in each step. A distinguishing feature of the tool is primarily providing spectra of generation possibilities ranging from full custom to automatic generation. ALG is not only designed to work as a standalone tool but also implemented to be the final step of an analog automation flow. The flow supports circuit level specification in addition to layout level user specifications, so that it can be integrated into an analog automation system. Another feature of ALG is its interaction with a layout adviser tool, namely, YASA. YASA performs sensitivity simulations using a spicelike simulator providing sensitivities of performance parameters with respect to circuit parameters.