Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
An optimal algorithm for floorplan area optimization
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Branch-and-bound placement for building block layout
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
DAC '93 Proceedings of the 30th international Design Automation Conference
Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Module placement on BSG-structure and IC layout applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Cluster refinement for block placement
DAC '97 Proceedings of the 34th annual Design Automation Conference
VLSI/PCB placement with obstacles based on sequence-pair
Proceedings of the 1997 international symposium on Physical design
Sequence-pair based placement method for hard/soft/pre-placed modules
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Rectilinear block placement using sequence-pair
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Arbitrary rectilinear block packing based on sequence pair
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
Slicing tree is a complete floorplan representation
Proceedings of the conference on Design, automation and test in Europe
Slicing floorplan design with boundary-constrained modules
Proceedings of the 2001 international symposium on Physical design
Revisiting floorplan representations
Proceedings of the 2001 international symposium on Physical design
Slicing floorplan with clustering constraints
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Module placement with boundary constraints using the sequence-pair representation
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
FAST-SP: a fast algorithm for block placement based on sequence pair
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
TCG: a transitive closure graph-based representation for non-slicing floorplans
Proceedings of the 38th annual Design Automation Conference
Floorplanning with abutment constraints and L-shpaed/T-shaped blocks baed on corner block list
Proceedings of the 38th annual Design Automation Conference
Twin binary sequences: a non-redundant representation for general non-slicing floorplan
Proceedings of the 2002 international symposium on Physical design
TCG-S: orthogonal coupling of P*-admissible representations for general floorplans
Proceedings of the 39th annual Design Automation Conference
Floorplanning with alignment and performance constraints
Proceedings of the 39th annual Design Automation Conference
Floorplan representations: Complexity and connections
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Constrained "Modern" Floorplanning
Proceedings of the 2003 international symposium on Physical design
Rectilinear block placement using B*-trees
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Multilevel floorplanning/placement for large-scale modules using B*-trees
Proceedings of the 40th annual Design Automation Conference
Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Rectilinear Block Placement Using B*-Trees
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An area-optimality study of floorplanning
Proceedings of the 2004 international symposium on Physical design
Practical slicing and non-slicing block-packing without simulated annealing
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Stairway compaction using corner block list and its applications with rectilinear blocks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Space-planning: placement of modules with controlled empty area by single-sequence
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
On handling arbitrary rectilinear shape constraint
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Robust fixed-outline floorplanning through evolutionary search
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Languages for system specification
Placement constraints in floorplan design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An orthogonal simulated annealing algorithm for large floorplanning problems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Ant colony system application to macrocell overlap removal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modern floorplanning based on fast simulated annealing
Proceedings of the 2005 international symposium on Physical design
Are floorplan representations important in digital design?
Proceedings of the 2005 international symposium on Physical design
Fixed-outline floorplanning based on common subsequence
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Fast evaluation of bounded slice-line grid
Journal of Computer Science and Technology
Joint exploration of architectural and physical design spaces with thermal consideration
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Temporal floorplanning using the T-tree formulation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Simultaneous block and I/O buffer floorplanning for flip-chip design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A fixed-die floorplanning algorithm using an analytical approach
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Using red-black interval trees in device-level analog placement with symmetry constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Fast floorplanning by look-ahead enabled recursive bipartitioning
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
LFF algorithm for heterogeneous FPGA floorplanning
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Placement with symmetry constraints for analog layout design using TCG-S
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal redistribution of white space for wire length minimization
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Interconnect estimation without packing via ACG floorplans
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
SoC test scheduling using the B-tree based floorplanning technique
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Floorplan and power/ground network co-synthesis for fast design convergence
Proceedings of the 2006 international symposium on Physical design
Solving hard instances of floorplacement
Proceedings of the 2006 international symposium on Physical design
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Wirelength optimization by optimal block orientation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Module placement for fault-tolerant microfluidics-based biochips
Proceedings of the 41st annual Design Automation Conference
Design space exploration for 3D architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A fast algorithm for rectilinear block packing based on selected sequence-pair
Integration, the VLSI Journal
A revisit to floorplan optimization by Lagrangian relaxation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Fast wire length estimation by net bundling for block placement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Analog placement with symmetry and other placement constraints
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Voltage island aware floorplanning for power and timing optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A new heuristic algorithm for rectangle packing
Computers and Operations Research
Fixed-outline floorplanning using robust evolutionary search
Engineering Applications of Artificial Intelligence
MP-trees: a packing-based macro placement algorithm for mixed-size designs
Proceedings of the 44th annual Design Automation Conference
Analog placement based on novel symmetry-island formulation
Proceedings of the 44th annual Design Automation Conference
Power-density aware floorplanning for reducing maximum on-chip temperature
MOAS'07 Proceedings of the 18th conference on Proceedings of the 18th IASTED International Conference: modelling and simulation
Chip placement in a reticle for multiple-project wafer fabrication
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multi-bend bus driven floorplanning
Integration, the VLSI Journal
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Floorplan considering interconnection between different clock domains
ICC'07 Proceedings of the 11th Conference on Proceedings of the 11th WSEAS International Conference on Circuits - Volume 11
Proceedings of the 2008 international symposium on Physical design
An improved particle swarm optimizer for placement constraints
Journal of Artificial Evolution and Applications - Particle Swarms: The Second Decade
Analog placement based on hierarchical module clustering
Proceedings of the 45th annual Design Automation Conference
DeFer: deferred decision making enabled fixed-outline floorplanner
Proceedings of the 45th annual Design Automation Conference
Effective decap insertion in area-array SoC floorplan design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Solving modern mixed-size placement instances
Integration, the VLSI Journal
Block flipping and white space distribution for wirelength minimization
Integration, the VLSI Journal
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Signal skew aware floorplanning and bumper signal assignment technique for flip-chip
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
T-trees: A tree-based representation for temporal and three-dimensional floorplanning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Parallel Simulated Annealing Approach for Floorplanning in VLSI
ICA3PP '09 Proceedings of the 9th International Conference on Algorithms and Architectures for Parallel Processing
Thermal-driven analog placement considering device matching
Proceedings of the 46th Annual Design Automation Conference
Performance-constrained voltage assignment in multiple supply voltage SoC floorplanning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Analog layout generator for CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Voltage-Island partitioning and floorplanning under timing constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analog placement based on symmetry-island formulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power-density aware floorplanning for reducing maximum on-chip temperature
MS '07 The 18th IASTED International Conference on Modelling and Simulation
Genetic algorithms for VLSI micro-cell layout area optimization based on binary tree
ACST '08 Proceedings of the Fourth IASTED International Conference on Advances in Computer Science and Technology
An effective approach for large scale floorplanning
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Hybrid algorithm for floorplanning using B*-tree representation
IITA'09 Proceedings of the 3rd international conference on Intelligent information technology application
DeFer: deferred decision making enabled fixed-outline floorplanning algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analog layout synthesis: recent advances in topological approaches
Proceedings of the Conference on Design, Automation and Test in Europe
Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Regularity-oriented analog placement with diffusion sharing and well island generation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Configurable multi-product floorplanning
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
UFO: unified convex optimization algorithms for fixed-outline floorplanning
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Regularity-constrained floorplanning for multi-core processors
Proceedings of the 2011 international symposium on Physical design
3D network-on-chip architectures using homogeneous meshes and heterogeneous floorplans
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
TCG: a transitive closure graph-based representation for general floorplans
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and Implementation of a Throughput-Optimized GPU Floorplanning Algorithm
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient package pin-out planning with system interconnects optimization for package-board codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast substrate noise aware floorplanning for mixed signal SOC designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Moving block sequence and organizational evolutionary algorithm for general floorplanning
CIS'05 Proceedings of the 2005 international conference on Computational Intelligence and Security - Volume Part I
Placement constraints and macrocell overlap removal using particle swarm optimization
ANTS'06 Proceedings of the 5th international conference on Ant Colony Optimization and Swarm Intelligence
A corner stitching compliant B*-tree representation and its applications to analog placement
Proceedings of the International Conference on Computer-Aided Design
Heterogeneous B*-trees for analog placement with symmetry and regularity considerations
Proceedings of the International Conference on Computer-Aided Design
A thermal aware floorplanning algorithm supporting voltage islands for low power SOC design
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
On improved least flexibility first heuristics superior for packing and stock cutting problems
SAGA'05 Proceedings of the Third international conference on StochasticAlgorithms: foundations and applications
Three-dimensional Integrated Circuits: Design, EDA, and Architecture
Foundations and Trends in Electronic Design Automation
LAYGEN II: automatic analog ICs layout generator based on a template approach
Proceedings of the 14th annual conference on Genetic and evolutionary computation
Hierarchical congregated ant system for bottom-up VLSI placements
Engineering Applications of Artificial Intelligence
Multi-bend bus-driven floorplanning considering fixed-outline constraints
Integration, the VLSI Journal
Variable-Order Ant System for VLSI multiobjective floorplanning
Applied Soft Computing
Double patterning lithography-aware analog placement
Proceedings of the 50th Annual Design Automation Conference
Simultaneous analog placement and routing with current flow and current density considerations
Proceedings of the 50th Annual Design Automation Conference
Multiple chip planning for chip-interposer codesign
Proceedings of the 50th Annual Design Automation Conference
Statistical thermal modeling and optimization considering leakage power variations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Routing analog ICs using a multi-objective multi-constraint evolutionary approach
Analog Integrated Circuits and Signal Processing
Template coding with LDS and applications of LDS in EDA
Analog Integrated Circuits and Signal Processing
Regularity-constrained floorplanning for multi-core processors
Integration, the VLSI Journal
A survey on B*-Tree-based evolutionary algorithms for VLSI floorplanning optimisation
International Journal of Computer Applications in Technology
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We present in this paper an efficient, flexible, and effective data structure, B*-trees for non-slicing floorplans. B*-trees are based on ordered binary trees and the admissible placement presented in [1]. Inheriting from the nice properties of ordered binary trees, B*-trees are very easy for implementation and can perform the respective primitive tree, operations search, insertion, and deletion in only O(1), O(1), and O(n) times while existing representations for non-slicing floorplans need at least O(n) time for each of these operations, where n is the number of modules. The correspondence between an admissible placement and its induced B*-tree is 1-to-1 (i.e., no redundancy); further, the transformation between them takes only linear time. Unlike other representations for non-slicing floorplans that need to construct constraint graphs for cost evaluation, in particular, the evaluation can be performed on B*-trees and their corresponding placements directly and incrementally. We further show the flexibility of B*-trees by exploring how to handle rotated, pre-placed, soft, and rectilinear modules. Experimental results on MCNC benchmarks show that the B*-tree representation runs about 4.5 times faster, consumes about 60% less memory, and results in smaller silicon area than the O-tree one [1]. We also develop a B*-tree based simulated annealing scheme for floorplan design; the scheme achieves near optimum area utilization even for rectilinear modules.