B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
A layout-aware synthesis methodology for RF circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
DAC '82 Proceedings of the 19th Design Automation Conference
ALI: A procedural language to describe VLSI layouts
DAC '82 Proceedings of the 19th Design Automation Conference
A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
IPRAIL: intellectual property reuse-based analog IC layout automation
Integration, the VLSI Journal - Special issue on analog and mixed-signal IC design and design methodologies
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Using red-black interval trees in device-level analog placement with symmetry constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
GA-SVM feasibility model and optimization kernel applied to analog IC design automation
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Analog layout generator for CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analog circuits optimization based on evolutionary computation techniques
Integration, the VLSI Journal
Analog layout synthesis: what's missing?
Proceedings of the 19th international symposium on Physical design
Analog Circuits and Systems Optimization based on Evolutionary Computation Techniques
Analog Circuits and Systems Optimization based on Evolutionary Computation Techniques
Analog Layout Synthesis: A Survey of Topological Approaches
Analog Layout Synthesis: A Survey of Topological Approaches
An automated design tool for analog layouts
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SIAR: splitting-graph-based interactive analog router
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
A fast and elitist multiobjective genetic algorithm: NSGA-II
IEEE Transactions on Evolutionary Computation
Automation of IC layout with analog constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Integrated Layout-Synthesis Approach for Analog ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
GENOM-POF: multi-objective evolutionary synthesis of analog ICs with corners validation
Proceedings of the 14th annual conference on Genetic and evolutionary computation
LAYGEN II: automatic analog ICs layout generator based on a template approach
Proceedings of the 14th annual conference on Genetic and evolutionary computation
Analog/RF and Mixed-Signal Circuit Systematic Design
Analog/RF and Mixed-Signal Circuit Systematic Design
ITRS 2011 analog EDA challenges and approaches
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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This paper describes a new multi-objective multi-constraint routing approach integrated in LAYGEN II, an analog integrated circuit layout generator based on template descriptions and evolutionary computation techniques. The approach gives special emphasis to the reusability of expert design knowledge and to the efficiency on retargeting operations. In order to increase the quality of routing solution, first, the placer processes the floorplan, automatically merging devices. Then, for routing, an optimization kernel is used, which consists of a modified version of the multi-objective evolutionary algorithm, NSGA-II. The Router optimizes all nets simultaneously and uses a built-in engine to evaluate each of the layout solutions. The automatic routing generation is detailed, and LAYGEN II is demonstrated for the layout generation of typical analog circuit structures, for the UMC 130 nm design process, and the results are successfully validated using the industrial grade verification Calibre® tool.