Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models

Authors:
Mukesh Ranjan;Wim Verhaegen;Anuradha Agarwal;Hemanth Sampath;Ranga Vemuri;Geoges Gielen
Affiliations:
-;-;-;-;-;-
Venue:
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Year:
2004

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Abstract

We present a new methodology for fast analog circuit synthesis, based on the use of parameterized layout generators and symbolic performance models (SPMs) in the synthesis loop. Fast layout generation is achieved by using efficient parameterized procedural layout generators. Fast performance estimation is achieved by using pre-compiled SPMs, stored asefficient DDD-like structures called Element Coefficient Diagrams. Techniques have been developed to include layout geometry effects in the SPMs. The accuracy and efficiency of theparasitic inclusion technique as well as the proposed methodology have been demonstrated by comparisons to traditional synthesis methods. The proposed methodology is used for thesynthesis of opamps and filters and is demonstrated to achieve effective performance closure.